MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 294

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
PMC Power-Down When the MPC8313E is a PCI Host
In this case the PCI device driver runs on the device e300 core and directly controls the PCI interface. The
e300 device driver also runs on e300 and controls the PMC module internally.
At initial power-up (POR) the host software running on the e300 is required to determine the power
management capabilities of all agents and initialize their PME context. It an agent is able to generate PME
it’s PME status must be cleared and its PME capability initialized.
Steps to power down an external PCI agent, and the device, are as follows:
5-86
8. The e300 sets existing PMC registers that allow power-down when the e300 enters nap or Sleep
9. The e300 stores context in SDRAM through MEMC, and sets MEMC up to allow SDRAM to
10. The e300 writes the PMCCR1[NEXT_STATE] value into PMCCR1[CURR_STATE], which is
11. The e300 asserts core_qreq_b, which is detected by the PMC. The PMC asserts STOP to the CSB
12. Before shutting off power to a portion of the die, PMC will turn on conditioning logic to isolate the
13. The PMC assets the core_qack_b signal to the e300 indicating it should enter Sleep mode. The
1. The PCI device driver executes code to save any PCI function context that would not otherwise
2. The PCI device driver enables external PCI agents to generate PCI_PME. The driver clears
3. In response to this PowerState field change the external PCI agent transitions itself to the new
4. The device detects the external agent’s PowerState change by polling the agent’s configuration
mode (PMCCR[DLPEN] and PMCCR[SLPEN]). Settings are based on the
PMCCR1[NEXT_STATE] field.
self-refresh during Sleep mode (DDR_SDRAM_CFG[SREN] = 1b).
reported in the PCIPMR1[Power_State]. e300 then clears the PMCIE event in the PMCER register.
It is important to note that the clearing of the PMCIE event should be done after changing the
current state to match the next state value. Only then PMCIE event can be cleared. e300 then sets
the PMCCR1[POWER_OFF] bit to 1 indicating that the external EXT_PWR_CTRL signal will be
toggled at the appropriate time to switch off external power.
arbiter, and waits for STOP_ACK. When the PMC receives STOP_ACK from the CSB arbiter, the
PMC asserts STOP to the DDR memory controller and DDR xlb2mg gasket and waits for their
STOP_ACKs. When the DDR controller's STOP_ACK is received, the PMC asserts an existing
pmc_stop_ddr_clk signal to stop the DDR clock.
powered-on region from the powered-off region.
external QUIESCE signal asserts. If PMCCR1[POWER_OFF] is set, EXT_PWR_CTRL signal is
negated to disable an external power switch shutting off VDD to a portion of the die.
survive the transition to the new PM state. The OS is required to disable the I/O and memory space
as well as bus mastering via the PCI Command register.
PME_Status in the agent and programs the D3Hot state into the PCI agent’s Power_State field.
power state and then updates its own PowerState field in its PCI configuration registers.
registers. This process is repeated until all external agents are in their low power states.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor