MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1171

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.4.4.4.9, 10-85
10.5.1.1, 10-87
10.5.1.2, 10-87
10.5.1.3, 10-88
10.5.1.3
With the use of a feature called address byte swap by setting LBCR[ABSWP], data and address muxing
can be swapped from the default available. Currently, LAD[0:31] carries A[0:31]. In case of 8-bit interface
with 8-bit addressing we do not get benefit of pin reduction with the available muxing. This is because,the
MSB of data is muxed with MSB of address. While 8-bit data required is LAD[0:7] and address required
is lower order bits A[24:31] we need to pull out all the 16 bits out of the device. For pin limited devices,
this feature can be used where LAD[0:7] is mapped to the lsb’s of A[24:31] and LAD[8:15] carries lsb+1
[16:23]. As a result while interfacing with 8 bit address and 8-bit data only LAD[0:7] is suffice with LALE
pin. The only drawback of this feature is that it does not support burst as all the address is latched from
LAD bus.
10.5.1.4, 10-88
10.5.4.5, 10-94
10.5.4.6, 10-94
Freescale Semiconductor
Multiplexed Address and Data to Save Maximum Pins in 8- to 16-Bit
Addressing
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
In this mode, as soon as UPM samples LUPWAIT negated on the rising edge of
the bus clock, it immediately generates an internal transfer acknowledge, which
allows a data transfer one bus clock cycle later. The generation of transfer
acknowledge is early because LUPWAIT is not re-synchronized. The
acknowledge occurs early or normally depending on whether the UPM was
already frozen in WAIT cycles or not. This feature allows the synchronous
negation of LUPWAIT to affect a data transfer, even if UTA, WAEN, and LAST
are set simultaneously.
Added paragraph to end of section as follows:
In case of UPM writes, program UTA and LAST in same RAM word. In case of
UPM reads, program UTA and LAST in consecutive or same RAM words.
In the first paragraph changed the first sentence to read: ‘... on LAD[0:15] (with
zero bits on LAD[16:31]) during address ...’.
Changed the title to read, ‘Non-Multiplexed Address and Data Buses’.
Added new Section 10.5.1.3 as follows:
Second paragraph, second sentence, changed ‘... 166-MHz bus frequency ...’ to
‘... 133-MHz bus frequency ...’.
After the first paragraph, added the following paragraph:
Note that operations specified by OP3 and OP4 (status read) should never be
skipped while erasing a NAND Flash device, because, in case that happens,
contention may arise on LGPL4. A possible case is that the next transaction from
eLBC may try to use that pin as an output and since the NAND Flash device might
already be driving it, contention will occur. In case OP3 and OP4 operations are
skipped, it may also happen that a new command is issued to the NAND Flash
device even when the device has not yet finished processing the previous request.
This may also result in unpredictable behavior.
After the first paragraph, added the following paragraph:
Note that operations specified by OP5 and OP6 (status read) should never be
skipped while programming a NAND Flash device, because, in case that happens,
Revision History
A-13