MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 532

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
Continued loop execution depends on the loop counter. If the counter is not zero, the next RAM word
executed is the loop start word. Otherwise, the next RAM word executed is the one after the loop end word.
Loops can be executed sequentially but cannot be nested. Also, special care must be taken:
10.4.4.4.6
The REDO function is useful for wait-state insertion in a long UPM routine that would otherwise need too
many RAM words. Setting the REDO bits of the RAM word to a nonzero value causes the UPM to
re-execute the current RAM word up to three more times, as defined in the REDO field of the current RAM
word.
Special care must be taken in the following cases:
10.4.4.4.7
Address lines can be controlled by the user-provided pattern in the UPM. The address multiplex (AMX)
bits in the RAM word can choose between driving the transaction address (AMX = 00), driving it
according to the multiplexing specified by the M
MAR (AMX = 11) on the address signals. The next address (NA) bit of the RAM word does not affect LA
signals, unless AMX = 00 and chooses the column address for NA = 1.
In all cases, LA[21:25] of the eLBC are driven by the five lsbs of the address selected by AMX, regardless
of whether the next address (NA) bit of the RAM word is used to increment the current address. The effect
of NA = 1 is visible only when AMX = 00 chooses the column address.
10-84
•
•
•
•
•
•
•
LAST and LOOP must not be set together.
Loop start word should not have an AMX change with regard to the previous word.
When UTA and REDO are set together, TA is asserted the number of times specified by the REDO
function.
When NA and REDO are set together, the address is incremented the number of times specified by
the REDO function.
When LOOP and REDO are set together, the loop mechanism works as usual and the line is
repeated according to the REDO function.
LAST and REDO must not be set together.
REDO should not be used within the exception routine.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Repeat Execution of Current RAM Word (REDO)
Address Multiplexing (AMX)
Read single-beat cycle
Read burst cycle
Write single-beat cycle
Write burst cycle
Refresh timer expired
RUN command
Request Serviced
Table 10-41. M
x
x
MR[AM] field (AMX = 10), or driving the contents of
MR Loop Field Use
Loop Field
WLF
WLF
RLF
RLF
RLF
TLF
Freescale Semiconductor