MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 932

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.2.1
UTMI was developed to specify a standard interface between USB 2.0 controllers and USB 2.0 PHY's.
This interface is made available to support applications that may use a UTMI-compliant PHY. UTMI+
extensions are not supported by the USB DR module. Functionality added by UTMI+ is available in the
ULPI interface. Only the integrated PHY uses the UTMI interface; therefore, there are no external UTMI
signals to be documented in this manual. The integrated USB PHY has four dedicated external signals,
which are only used when the MPC8313E is a host: USBDR_DRIVE_VBUS, USBDR_PWRFAULT,
USBDR_PCTL0, and USBDR_PCTL1. These signals are also part of ULPI Interface as described below.
16.2.2
The ULPI (UTMI low pin count interface) is a reduced pin-count (12 signals) extension of the UTMI+
specification. Pin count is reduced by converting relatively static signals to register bits, and providing a
bidirectional, generic data bus that carries USB and register data. This interface minimizes pin count
requirements for external PHYs.
16-4
USBDR_NXT
USBDR_DIR
Signal
USBDR_PCTL1
UTMI Interface
ULPI Interface
USBDR_CLK
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Signal
I/O
I
I
transfer to USB port, it drives USBDR_DIR high to take ownership of the bus. When the PHY
has no data to transfer it drives USBDR_DIR low and monitors the bus for link activity. The PHY
pulls USBDR_DIR high whenever the interface cannot accept data from the link.
to the PHY, USBDR_NXT indicates when the current byte has been accepted by the PHY. The
USB port places the next byte on the data bus in the following clock cycle. When the PHY is
sending data to USB port, USBDR_NXT indicates when a new byte is available for USB port
to consume.
Direction. USBDR_DIR controls the direction of the data bus. When the PHY has data to
Next data. The PHY asserts USBDR_NXT to throttle the data. When USB port is sending data
Meaning
Meaning
Timing Synchronous to PHY_CLK.
Timing Synchronous to PHY_CLK.
Table 16-1. USB External Signals (continued)
State
State
Table 16-2
Table 16-2. ULPI Signal Descriptions
Asserted—PHY has data to transfer to the link.
Negated—PHY has no data to transfer.
Asserted—PHY is ready to transfer byte.
Negated—PHY is not ready.
I/O
O
I
describes the signals for the ULPI interface.
ULPI—Use as USBDR_PCTL1USB_VDDA
ULPI—Use as USBDR_CLK
Description
Description
Freescale Semiconductor