MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 588

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
13-6
PCI_C/BE[3:0]
PCI_AD[31:0]
PCI_DEVSEL
Signal
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 13-3. PCI Interface Signals—Detailed Signal Descriptions (continued)
I/O
I/O PCI address/data bus. During an address phase, these signals contain a physical address. During a
I/O PCI bus command/byte enable.
I/O PCI device select.
O
O
O
I
I
I
data phase, these signals contain the data bytes.
Outputs for the bi-directional PCI address/data bus.
Inputs for the bi-directional PCI address/data bus.
Outputs for the bi-directional command/byte enable.
Inputs for the bi-directional command/byte enable.
Outputs for the bi-directional device select.
Inputs for the bi-directional device select.
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
State
State
State
State
State
State
Asserted/Negated—Represents the physical address during the address phase of a PCI
Asserted/Negated—Represents the address to be decoded as a check for device select
Asserted/Negated—During the address phase, PCI_CBE[3:0],define the bus command.
Byte enables determine which byte lanes carry meaningful data for PCI bus data phases.
The PCI_CBE[0] signal applies to the LSB.
Asserted/Negated—During the address phase, PCI_CBE[3:0], indicate the command
that another master is sending. During the PCI bus data phase, PCI_CBE[3:0], indicate
which byte lanes are valid.
Asserted—The PCI controller has decoded the address and is the target of the current
Negated—The PCI controller has decoded the address and is not the target of the current
Asserted—Some PCI agents (other than this PCI controller) have decoded its address as
Negated—No PCI agent has been selected.
transaction. During the data phase(s) of a PCI transaction, the PCI address/data bus
contain the data being written.
PCI_AD[7:0] define the LSB and, PCI_AD[31:24] define the MSB.
during the address phase of a PCI transaction or the data being received during the
data phase(s) of a PCI transaction.
PCI_AD[7:0] define the LSB and, PCI_AD[31:24] define the MSB.
access.
access.
the target of the current access.
Description
Freescale Semiconductor