MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 240

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
Table 5-34
5.4.4.2
The system watchdog count register (SWCNR), shown in
counter value. SWCNR is a read-only register. Writes to SWCNR have no effect and terminate without
transfer error exception.
5-32
16–28
0–15
Bits
Offset 0x8
Reset 0
29
30
31
W
R
0
SWEN
SWPR
SWTC
Name
SWRI
defines the bit fields of SWCRR.
0
—
System Watchdog Count Register (SWCNR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0
0
Software watchdog time count
The SWTC field contains the modulus that is reloaded into the watchdog counter by a service sequence.
When a new value is loaded into SWCRR[SWTC], the software watchdog timer is not updated until the
servicing sequence is written to the SWSRR. If SWCRR[SWEN] is loaded with 0, the modulus counter
does not count. The new value is also used at the next and all subsequent reloads. Reading the SWCRR
register returns the value in the system watchdog control register. Reset initializes the SWCRR[SWTC]
field to 0xFFFF.
Note: The prescaler counter is reset any time a new value is loaded into the watchdog counter and also
Write reserved, read = 0
Watchdog enable bit
Enables the watchdog timer. The reset value directly depends on the value of the RCWHR[SWEN] bit. It
should be cleared by software after a system reset to disable the software watchdog timer. When the
watchdog timer is disabled, the watchdog counter and prescaler counter are held in a stopped state.
0 Watchdog timer disabled
1 Watchdog timer enabled
Note: After software writes the SWRI bit, the state of SWEN cannot be changed.
Software watchdog reset/interrupt select bit
A WDT timer out causes either a hard reset or machine check interrupt to the core.
0 Software watchdog timer causes a machine check interrupt to the core
1 Software watchdog timer causes a hard reset
Software watchdog counter prescale bit
Controls the divide-by-65,536 WDT counter prescaler
0 The WDT counter is not prescaled.
1 The WDT counter clock is prescaled.
0
0
during reset.
Figure 5-20. System Watchdog Count Register (SWCNR)
0
0
—
0
0
Table 5-34. SWCRR Bit Settings
0
0
0
0
0
15 16
0
Description
1
Figure
1
1
5-20, provides visibility to the watchdog
1
1
1
1
SWCN
1
1
Freescale Semiconductor
1
1
Access: Read only
1
1
1
1
31
1