MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1092

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

I
17.3.1.4
I2CSR is shown in
Table 17-7
17-8
2
C Interfaces
Bits
0
1
2
3
4
5
BCSTM Broadcast match. Writing to the I2C n CR automatically clears this bit.
MAAS
Name
SRW
MCF
MBB
MAL
describes the bit settings of the I2CnSR.
Offset 0x0_300C
Reset
I
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
C n Status Register (I2C n SR)
W
R
Data transfer. When one byte of data is transferred, the bit is cleared. It is set by the falling edge of the 9th
0 Byte transfer in progress. MCF is cleared under the following conditions:
1 Byte transfer is completed
Addressed as a slave. When the value in I2C n ADR matches the calling address or when the calling address
is the broadcast address and broadcast mode is enabled (I2C n CR[BCST] is set), this bit is set. The
processor is interrupted if I2C n CR[MIEN] is set. Next, the processor must check the SRW bit and set
I2C n CR[MTX] accordingly. Writing to the I2C n CR automatically clears this bit.
0 Not addressed as a slave
1 Addressed as a slave
Bus busy. Indicates the status of the bus. When a START condition is detected, MBB is set. If a STOP
condition is detected, it is cleared.
0 I
1 I
Arbitration lost. Automatically set when the arbitration procedure is lost. Note that the device does not
automatically retry a failed transfer attempt.
0 Arbitration is not lost. Can only be cleared by software
1 Arbitration is lost
0 There has not been a broadcast match.
1 The calling address matches with the broadcast address and broadcast mode is enabled. This is also
Slave read/write. When MAAS is set, SRW indicates the value of the R/W command bit of the calling
address, which is sent from the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave. This bit is valid only when both of the following conditions are
By checking SRW, the processor can select slave transmit/receive mode according to the command of the
master.
clock of a byte transfer.
set if this I
true:
Figure
• When I2C n DR is read in receive mode or when I2C n DR is written in transmit mode.
• After a start sequence is recognized by the I
2
2
• A complete transfer occurred and no other transfers have been initiated.
• The I
MCF
C bus is idle
C bus is busy
0
1
2
C interface is configured as a slave and has an address match.
17-5.
2
C drives an address of all 0s.
MAAS
0
1
Figure 17-5. I
Table 17-7. I2C n SR Field Descriptions
MBB
0
2
2
C n Status Register (I2C n SR)
MAL
0
3
Description
BCSTM
2
C controller in slave mode.
0
4
SRW
0
5
MIF
0
6
Access: Mixed
Freescale Semiconductor
RXAK
1
7