MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 186

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Reset, Clocking, and Initialization
4.3.2.2.6
The eTSEC2 mode reset configuration word field, shown in
eTSEC2 controller (enhanced three-speed Ethernet controller interface).
4.3.2.2.7
The true little endian reset configuration word field, shown in
operates in big-endian mode or true little-endian mode at reset.
4-20
Reset Configuration
Reset Configuration
Word High Register
Word High Register
(RCWHR) Bits
(RCWHR) Bit
19–21
28
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
eTSEC2 Mode
The reset value of the system I/O configuration register high (SICRH)
depends on the setting of TSEC2M. This is used to avoid contention in
systems not using TBI or RTBI modes. In non-TBI modes, device signals
which have additional functions are set to be in a non-TSEC function, thus
not driven during and after reset. The function of these signals can be
changed by writing to this register during system initialization. See
Section 5.3.2.6, “System I/O Configuration Register High (SICRH).”
e300 Core True Little-Endian
Field Name
Field Name
TSEC2M
TLE
Table 4-17. eTSEC2 Mode Configuration
Table 4-18. e300 Core True Little-Endian
(Binary)
(Binary)
Value
Value
000
001
010
011
100
101
110
111
0
1
The eTSEC2 controller operates in the MII protocol, using only four
transmit data signals and four receive data signals.
The eTSEC2 controller operates in the RMII protocol, using only two
transmit data signals and two receive data signals.
Reserved
The eTSEC2 controller operates in the RGMII protocol, using four
transmit data signals and four receive data signals.
Reserved
The eTSEC2 controller operates in the RTBI protocol, using only four
transmit data signals and four receive data signals.
The eTSEC2 controller operates in the SGMII protocol, using the
on-chip PHY.
Reserved
Big-endian mode
True little-endian mode
NOTE
Table
Table
4-17, selects the protocol used by the
4-18, selects whether the e300 core
Meaning
Meaning
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