MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 351

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
Program
Floating-point
unavailable
Decrementer
Critical interrupt
Reserved
System call
Trace
Reserved
Performance
monitor
Instruction
translation miss
Data load
translation miss
Data store
translation miss
Instruction
address
breakpoint
Interrupt Type
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
00700
00800
00900
00A00
00B00–00BFF
00C00
00D00
00E00
00F00
01000
01100
01200
01300
Vector Offset
(hex)
Table 7-7. Exceptions and Interrupts (continued)
Caused by one of the following exception conditions, which correspond to bit settings in
SRR1 and arise during execution of an instruction.
Floating-point enabled exception—A floating-point enabled exception condition is
generated when the following condition is met:
Caused by an attempt to execute a floating-point instruction (including floating-point load,
store, and move instructions) when the floating-point available bit (MSR[FP]) is cleared.
Occurs when DEC[0] changes from 0 to 1. This interrupt is enabled with MSR[EE].
Taken when cint is asserted and MSR[CE] = 1.
Occurs when a System Call (sc) instruction is executed.
Taken when MSR[SE] =1 or when the currently completing instruction is a branch and
MSR[BE] =1.
The e300 core does not generate an interrupt to this vector. Other devices may use this
vector for floating-point assist interrupts.
Caused when a configured PM counter using the pm_event_in to transition overflows.
Caused when the effective address for an instruction fetch cannot be translated by the
ITLB.
Caused when the effective address for a data load operation cannot be translated by the
DTLB.
Caused when the effective address for a data store operation cannot be translated by the
DTLB, or when a DTLB hit occurs and the change bit in the PTE must be set due to a data
store operation.
Occurs when the address (bits 0–29) in the IABR matches the next instruction to complete
in the completion unit, and IABR[30] is set. Note that the e300 core also implements
IABR2, which functions identically to IABR.
• FPSCR[FEX] is set by the execution of a floating-point instruction that causes an
• Illegal instruction—An illegal instruction program interrupt is generated when execution
• Privileged instruction—A privileged instruction program interrupt is generated when the
• Trap—A trap type program interrupt is generated when any of the conditions specified
enabled exception or by the execution of one of the Move to FPSCR instructions that
results in both an exception condition bit and its corresponding enable bit being set in
the FPSCR.
of an instruction is attempted with an illegal opcode or illegal combination of opcode and
extended opcode fields (including PowerPC instructions not implemented in the core),
or when execution of an optional instruction not provided in the core is attempted (these
do not include those optional instructions that are treated as no-ops).
execution of a privileged instruction is attempted and the MSR register user privilege
bit, MSR[PR], is set. In the e300 core, this interrupt is generated for mtspr or mfspr with
an invalid SPR field if SPR[0] = 1 and MSR[PR] = 1. This may not be true for all cores
that implement the PowerPC architecture.
in a trap instruction are met.
(MSR[FE0] | MSR[FE1]) and FPSCR[FEX] is 1.
Exception Conditions
—
e300 Processor Core Overview
7-33