MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1001

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Super-imposed on this requirement is that USB 2.0 hubs manage full- and low-speed transactions via a
micro-frame pipeline (see start- (SS) and complete- (CS) splits illustrated in
direct projection of the frame boundary model into the host controller interface schedule architecture
creates tension (complexity for both hardware and software) between the frame boundaries and the
scheduling mechanisms required to service the full- and low-speed transaction translator periodic
pipelines.
The simple projection, as
scheduling on both the beginning and end of a frame. In order to reduce the complexity for hardware and
software, the host controller is required to implement a one micro-frame phase shift for its view of frame
boundaries. The phase shift eliminates the beginning of frame and frame-wrap scheduling boundary
conditions.
The implementation of this phase shift requires that the host controller use one register value for accessing
the periodic frame list and another value for the frame number value included in the SOF token. These two
values are separate, but tightly coupled. The periodic frame list is accessed via the Frame List Index
Register (FRINDEX). Bits FRINDEX[2–0], represent the micro-frame number. The SOF value is coupled
to the value of FRINDEX[13–3]. Both FRINDEX[13–3] and the SOF value are incremented based on
FRINDEX[2–0]. It is required that the SOF value be delayed from the FRINDEX value by one
micro-frame. The one micro-frame delay yields a host controller periodic schedule and bus frame
boundary relationship as illustrated in
the periodic start and complete-split transactions for full-and low-speed periodic endpoints, using the
natural alignment of the periodic schedule interface.
Figure 16-46
frame boundaries. To aid the presentation, two terms are defined. The host controller's view of the
1-millisecond boundaries is called H-Frames. The high-speed bus's view of the 1-millisecond boundaries
is called B-Frames.
Freescale Semiconductor
Micro-Frame
FS/LS Bus
Numbers
HS Bus
illustrates how periodic schedule data structures relate to schedule frame boundaries and bus
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 16-45. Frame Boundary Relationship Between HS Bus and FS/LS Bus
7
SS
Boundary
Frame
Figure 16-45
0
1
CS
Figure
illustrates, introduces frame-boundary wrap conditions for
2
16-46. This adjustment allows software to trivially schedule
CS
CS
3
SS
4
CS
5
CS
6
CS
Figure
Universal Serial Bus Interface
7
CS
16-45). A simple,
0
CS
1
16-73