MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 405

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

9.4.1.3
DDR SDRAM timing configuration register 3, shown in
time, which is combined with TIMING_CFG_1[REFREC] to determine the full refresh recovery time.
Freescale Semiconductor
13–15
16–17
18–20
21–23
24–28
29–31
9–11
Bits
12
8
ROW_BITS_CS_ n Number of row bits for SDRAM on chip select n . See
COL_BITS_CS_ n
BA_BITS_CS_ n
ODT_WR_CFG
ODT_RD_CFG
AP_ n _EN
DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
—
—
—
Table 9-7. CS n _CONFIG Field Descriptions (continued)
Chip select n auto-precharge enable
0 Chip select n is only auto-precharged if global auto-precharge mode is enabled
1 Chip select n always issues an auto-precharge for read and write transactions.
3 cycles for ODT_RD_CFG to be enabled. ODT should only be used with DDR2 memories.
000 Never assert ODT for reads
001 Assert ODT only during reads to CS n
010 Assert ODT only during reads to other chip selects
011 Reserved
100 Assert ODT for all reads
101–111 Reserved
Reserved
ODT for writes configuration. Note that write latency plus additive latency must be at least
3 cycles for ODT _WR_CFG to be enabled. ODT should only be used with DDR2 memories.
000 Never assert ODT for writes
001 Assert ODT only during writes to CS n
010 Assert ODT only during writes to other chip selects
011 Reserved
100 Assert ODT for all writes
101–111 Reserved
Number of bank bits for SDRAM on chip select n . These bits correspond to the sub-bank bits
driven on MBA n in
00 2 logical bank bits
01 3 logical bank bits
10–11 Reserved
Reserved
000 12 row bits
001 13 row bits
010 14 row bits
011 15 row bits
000–111 Reserved
Reserved
Number of column bits for SDRAM on chip select n. For DDR, the decoding is as follows:
000 8 column bits
001 9 column bits
010 10 column bits
011 11 column bits
100–111 Reserved
ODT for reads configuration. Note that CAS latency plus additive latency must be at least
(DDR_SDRAM_INTERVAL[BSTOPRE] = 0).
Table 9-27
and
Table
Figure
9-28.
Description
9-4, sets the extended refresh recovery
Table 9-27
and
Table 9-28
DDR Memory Controller
for details.
9-11