MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 783

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

is sensed. During the final one-third of the IPG, CRS is ignored and the transmission begins once IPG is
timed. The two-thirds/one-third ratio is the recommended value.
15.5.3.4.3
While transmitting a packet in half-duplex mode, the eTSEC is sensitive to COL. If a collision occurs, it
aborts the packet and outputs the 32-bit jam sequence. The jam sequence is comprised of several bits of
the CRC, inverted to guarantee an invalid CRC upon reception. A signal is sent to the system indicating
that a collision occurred and that the start of the frame is needed for retransmission. The eTSEC then backs
off of the medium for a time determined by the truncated binary exponential back off (BEB) algorithm.
Following this back-off time, the packet is retried. The back-off time can be skipped if configured through
the half-duplex register. However, this is non-standard behavior and its use must be carefully applied.
Should any one packet experience excessive collisions, the packet is aborted. The system should flush the
frame and move to the next one in line. If the system requests to send a packet while the eTSEC is deferring
to a carrier, the eTSEC simply waits until the end of the carrier event and the timing of IPG before it honors
the request.
If packet transmission attempts experience collisions, the eTSEC outputs the jam sequence and waits some
amount of time before retrying the packet. This amount of time is determined by a controlled
randomization process called truncated binary exponential back-off. The amount of time is an integer
number of slot times. The number of slot times to delay before the nth retransmission attempt is chosen as
a uniformly-distributed random integer r in the range:
So after the first collision, the eTSEC backs off either 0 or 1 slot times. After the fifth collision, the eTSEC
backs off between 0 and 32 slot times. After the tenth collision, the maximum number of slot times to back
off is 1024. This can be adjusted through the half-duplex register. An alternate truncation point, such as 7
for instance, can be programmed. On average, the MAC is more aggressive after seven collisions than
other stations on the network.
15.5.3.4.4
Packet flow can be dealt with in a number of ways within eTSEC. A default retransmit attempt limit of 15
can be reduced using the half-duplex register. The slot time or collision window can be used to gate the
retry window and possibly reduce the amount of transmit buffering within the system. The slot time for
10/100 Mbps is 512 bit times. Because the slot time begins at the beginning of the packet (including
preamble), the end occurs around the 56th byte of the frame data. Slot time in 1000-Mbps mode is not
supported.
Full-duplex flow control is provided for in IEEE 802.3x. Currently the standard does not address flow
control in half-duplex environments. Common in the industry, however, is the concept of back pressure.
The eTSEC implements the optional back pressure mechanism using the raise carrier method. If the system
receive logic wishes to stop the reception of packets in a network-friendly way, transmit half-duplex flow
control (THDF) is set (TCTRL[THDF]). If the medium is idle, the eTSEC raises carrier by transmitting
preamble. Other stations on the half-duplex network then defer to the carrier.
In the event the preamble transmission happens to cause a collision, the eTSEC ensures the minimum
96-bit presence on the wire, then drops preamble and waits a back-off time depending on the value of the
Freescale Semiconductor
0 ≤ r ≤ 2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Handling Packet Collisions
Controlling Packet Flow
k
, where k = min(n,10).
Enhanced Three-Speed Ethernet Controllers
15-65