MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 838

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Offset eTSEC1:0x2_4E40+8× n
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Enhanced Three-Speed Ethernet Controllers
Table 15-122
15.5.3.10.13 Timer Fixed Interval Period Register (TMR_FIPER1–3)
Timer fixed interval period pulse generator register. It is used to generate periodic pulses. This register is
reset with 0xFFFF_FFFF to prevent any false pulse upon initialization. The down count register loads the
value programmed in the fixed period interval (FIPER). FIPER register must be programmed before the
timer is enabled. At every tick of the timer accumulator overflow, the counter decrements by the value of
TMR_CTRL[TCLK_PERIOD]. It generates a pulse when the down counter value reaches zero. It reloads
the down counter in the cycle following a pulse.
Should a user wish to use the TMR_FIPER1 register to generate a 1 PPS event, the following setup should
be used:
The eTSEC will then wait for TMR_ALARM1 to expire before enabling the count down of
TMR_FIPER1. The end result will be that TMR_FIPER1 will pulse every second after the original timer
ALARM1 expired.
Note:
In the case where the PPS signals are required to be phased aligned to the prescale output clock, the alarm
value should be configured to 1 clock period less than the wanted value.
In order to keep tracking the prescale output clock, each time before enabling the FIPER, the user must
reset the FIPER by writing a new value to the register. The ratio between the prescale register value and
the FIPER value should be devisable by the clk period.
15-120
0–63
Bits
W
R
•
•
•
0
Program TMR_FIPER1 to a value that will generate a pulse every second,
Program TMR_ALARM1 to the correct time for the first PPS event
Enable the timer
ALARM_H/L Alarm time comparator register. The corresponding alarm event in TMR_TEVENT is set when the
Name
describes the fields of the TMR_ALARMn_H/L register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
current time counter becomes equal to or greater than the alarm time compare value in
TMR_ALARM n _L/H. Writing the TMR_ALARM n _L register deactivates the alarm event after it has
fired. Writing the TMR_ALARM n _L followed by the TMR_ALARM n _H register rearms the alarm
function with the new compare value.
The value programmed in this register must be an integer multiple of TMR_CTRL[TCLK_PERIOD] in
order to get correct result. This register is reset to all ones to avoid false alarm after reset.
In FS mode the alarm trigger is used as an indication to the fiper start down counting. Only alarm 1
supports this mode. In FS mode, alarm polarity bit should be configured to 0 (rising edge).
Table 15-122. TMR_ALARM n _H/L Register Field Descriptions
Figure 15-114. TMR_ALARM1-2_H/L Register Definition
ALARM_H
31 32
Description
ALARM_L
Freescale Semiconductor
Access: Read/Write
63