MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 883

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.6.4
This section describes the quality of service support features of this device. It includes a parser which
extracts vital packet properties and passes then to the filer which essentially acts as a frame classifier.
15.6.4.1
The receive parser parses the incoming frame data and generates filer properties and frame control block
(FCB). The receive parser composes of the Ethernet header parser and L3/L4 parser.
The Ethernet header parser parses only L2 (ethertype) headers. It is enabled by RCTRL[PRSDEP] != 0. It
has the following key features:
Freescale Semiconductor
Bytes
2–3
4–5
6–7
•
•
•
•
•
•
•
Extraction of 48-bit MAC destination and source addresses
Extraction and recognition of the first 2-byte ethertype field
Extraction and recognition of the final 2-byte ethertype field
Extraction of 2-byte VLAN control field
Walk through MPLS stack and find layer 3 protocol
Walk through VLAN stack and find layer 3 protocol
Recognition of the following ethertypes for inner layer parsing
— LLC and SNAP header
8–15
0–15
0–15
Bits
0–1
2–7
Quality of Service (QoS) Provision
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Receive Parser
VLCTL
Name
PRO
RQ
—
—
Table 15-153. Rx Frame Control Block Descriptions (continued)
Reserved
Receive queue index. This index was selected by the eTSEC Rx Filer (from a matching Filer rule’s
RQCTRL[Q] field) when it accepted the associated frame. If filing is not enabled, RQ is zero. Note
that the 3 least significant bits of RQ correspond with the RxBD ring index whenever
RCTRL[FSQEN] = 0.
If IP = 1, PRO is set as follows:
If IP = 0, PRO is undefined.
Note that the eTSEC parser logic stops further parsing when encountering an IP datagram that
has indicated that it has fragmented the upper layer protocol. This in general means that there is
likely no layer 4 header following the IP header and extension headers. eTSEC leaves the
RxFCB[PRO] and RQFPR[L4P] fields 0xFF in this case, which usually means that there was no IP
header seen. In this case RxFCB[IP] and optionally RxFCB[IP6] is set. IP header checksumming
operates and performs as intended. Most of the time, the eTSEC updates the RxFCB[PRO] field
and RQFPR[L4P] fileds with whatever value was found in the protocol field of the IP header. See
Section 15.5.3.3.8, “Receive Queue Filer Table Property Register
RQFPR.
Reserved
VLAN control word as per IEEE Std. 802.1Q. The lower 12 bits comprise the VLAN identifier. Valid
only if VLN = 1.
• PRO=0xFF for a fragment header or a back to back route header
• PRO=0x nn for an unrecognized header, where nn is the next protocol field
• PRO=(TCP/UDP header), as defined in the IANA specification, if TCP or UDP header is found
Description
Enhanced Three-Speed Ethernet Controllers
(RQFPR),” for a description of
15-165