MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1118

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DUART
Table 18-10
The bits contained in the UIIR registers are described in
18.3.1.6
UFCR is used to enable and clear the receiver and transmitter FIFOs, set a receiver FIFO trigger level to
control the received data available interrupt, and select the type of DMA signaling.
UFCR bits cannot be programmed unless FIFO enable bits are set. When changing from FIFO mode to
16450 mode (non-FIFO mode) and vice versa, data is automatically cleared from the FIFOs.
After all of the bytes in the receiver FIFO are cleared, the receiver internal shift register is not cleared.
Similarly, the bytes are cleared in the transmitter FIFO, but the transmitter internal shift register is not
cleared. Both TFR and RFR are self clearing.
18-10
Bits
0–1
2–3
5–6
IID3–
0001
0110
0100
1100
0010
0000
IID0
4
7
IID2–IID1 Interrupt ID bits identify the highest priority pending interrupt as indicated in
Priority
Highest
Second
Second
Name
Fourth
Level
Third
IID3
IID0
FE
—
—
describes the fields of the UIIR.
FIFO Control Registers (UFCR1 and UFCR2)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Received data available Receiver data available or trigger level
FIFOs enabled. Reflects the setting of UFCR[FEN].
Reserved
Interrupt ID bits identify the highest priority interrupt that is pending as indicated in
set along with IID2 only when a time out interrupt is pending for FIFO mode.
IID0 indicates when an interrupt is pending.
0 The UART has an active interrupt ready to be serviced.
1 No interrupt is pending.
Receiver line status
Character time-out
Interrupt Type
MODEM status
UTHR empty
—
Table 18-10. UIIR Field Descriptions
Table 18-11. UIIR IID Bits Summary
Overrun error, parity error, framing error, or
break interrupt
reached in FIFO mode.
No characters were removed from or input to
the receiver FIFO during the last four
character times and at least one character is
in the receiver FIFO.
Transmitter holding register is empty.
CTS input value changed since last read of
UMSR.
Interrupt Description
Description
Table
—
18-11.
Reading the line status register
Reading the receiver buffer
register or if the number of
bytes in the receiver FIFO
drops below the trigger level.
Reading the receiver buffer
register
Reading UIIR or writing to
UTHR
Reading UMSR
How To Reset Interrupt
Table
Freescale Semiconductor
18-11.
Table
—
18-11. IID3 is