MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 812

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.6.30 Transmit Deferral Packet Counter (TDFR)
Figure 15-81
Table 15-85
15.5.3.6.31 Transmit Excessive Deferral Packet Counter (TEDF)
Figure 15-82
Table 15-86
15-94
20–31
0–19
Bits
Offset eTSEC1:0x2_46F4; eTSEC2:0x2_56F4
Reset
Offset
Reset
20–31
0–19
Bits
W
W
R
R
Name
TDFR
0
0
eTSEC1:0x2_46F8; eTSEC2:0x2_56F8
—
describes the fields of the TDFR register.
describes the fields of the TEDF register.
Name
TEDF
describes the definition for the TDFR register.
describes the definition for the TEDF register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 15-82. Transmit Excessive Deferral Packet Counter Register Definition
—
Reserved
Transmit deferral packet counter. Increments for each frame, which was deferred on its first transmission
attempt. This count does not include frames involved in collisions.
Figure 15-81. Transmit Deferral Packet Counter Register Definition
Reserved
an excessive period of time (3036 byte times).
Transmit excessive deferral packet counter. Increments for frames aborted which were deferred for
Table 15-85. TDFR Field Descriptions
Table 15-86. TEDF Field Descriptions
—
—
All zeros
All zeros
Description
Description
19 20
19 20
Freescale Semiconductor
TDFR
TEDF
Access: Read/Write
Access: Read/Write
31
31