MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1136

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Serial Peripheral Interface
To start exchanging data, the processor core writes the data to be sent into the SPITD register. The SPI then
generates programmable clock pulses on SPICLK for each character. It shifts Tx data out on the SPI
master-out slave-in (SPIMOSI) and Rx data in on the SPI master-in slave-out (SPIMISO) simultaneously.
During transmission, the core is responsible for supplying the data whenever the SPI requests it to ensure
smooth operation. After the last data (LST command and data afterwards), the first character written to
SPITD acts as a start command for the SPI.
The SPI continues transmitting and receiving characters until SPCOM[LST] is set or an error occurs.
The SPI sets SPIE[NF] to issue a maskable interrupt to the interrupt controller whenever its transmit buffer
is not full. It also sets the NF bit after sending the last word. In response, the core should read the exception
flags that relate to the last word. The SPI sets SPIE[NE] to issue a maskable interrupt to the interrupt
controller whenever the receiver buffer has been filled with data.
19.2.3.2
In slave mode, the SPI receives messages from an SPI master and sends a simultaneous reply. The slave’s
SPISEL must be asserted before Rx clocks are recognized. Once SPISEL is asserted, SPICLK becomes an
input from the master to the slave. SPICLK can be any frequency from DC to input clock/2.
To prepare for data transfers, the core writes data to be sent into the SPITD register. Once SPISEL is
asserted, the slave shifts data out from SPIMISO and in through SPIMOSI. The SPI sets the NF bit of the
SPIE register and a maskable interrupt is issued when a full buffer finishes receiving and sending or after
an error. The SPI continues reception until SPISEL is negated.
19-4
SPI as a Slave Device
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 19-2. Single-Master/Multi-Slave Configuration
Master SPI
SPIMOSI
SPIMISO
SPICLK
GPIOx
GPIOy
GPIOz
SPIMOSI
SPIMISO
SPICLK
SPISEL
SPIMOSI
SPIMISO
SPICLK
SPISEL
SPIMOSI
SPIMISO
SPICLK
SPISEL
Slave 1
Slave 2
Slave 0
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