MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 96

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Overview
1.2.8
The IPIC implements the necessary functions to provide a flexible solution for general-purpose interrupt
control. The IPIC includes the following features:
1.2.9
The inter-IC (IIC or I
bus that provides a simple, efficient method of data exchange between the system and other devices, such
as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCDs. The two-wire bus
minimizes the interconnections between devices. The synchronous, multi-master bus of the I
connection of additional devices to the bus for expansion and system development.
The I
prevents data corruption if two or more masters attempt to control the bus simultaneously. This feature
allows for complex applications with multiprocessor control. The I
transmitter/receiver unit, clocking unit, and control unit. The I
on-chip filtering rejects spikes on the bus.
The I
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C controller is a true multi-master bus which includes collision detection and arbitration that
C interfaces include the following features:
Functional and programming models are compatible with the MPC8260 interrupt controller
Support for external and internal discrete interrupt sources
Support for one external (optional) and seven internal machine checkstop interrupt sources
Programmable highest priority request
Two programmable priority mixed groups of four on-chip and four external interrupt signals with
two priority schemes for each group: grouped and spread
Two programmable priority internal groups of eight on-chip interrupt signals with two priority
schemes for each group: grouped and spread
Priority interrupts can be programmed to support a critical (cint) or system management (smi)
interrupt type
External and internal interrupts directed to a host processor
Unique vector number for each interrupt source
Ability to redirect interrupts to external PCI_INTA pin when in core disable mode
Two-wire interface
Multi-master operational
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Bus busy detection
Software-programmable clock frequency
Software-selectable acknowledge bit
On-chip filtering for spikes on the bus
Address broadcasting supported
Integrated Programmable Interrupt Controller (IPIC)
Dual I
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
2
C Interfaces
C) bus is a two-wire—serial data (SDA) and serial clock (SCL)—bidirectional serial
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C unit supports general broadcast mode and
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C controller consists of a
Freescale Semiconductor
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C allows the