MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 520

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.4.4
UPMs are flexible interfaces that connect to a wide range of memory devices. At the heart of each UPM
is an internal RAM array that specifies the logical value driven on the external memory control signals
(LCSn, LBS[0:1] and LGPL[0:5]) for a given clock cycle. Each word in the RAM array provides bits that
allow a memory access to be controlled with a resolution of up to one quarter of the external bus clock
period on the byte-select and chip-select lines. A gap of 2 dead LCLK cycles is present on the UPM
interface between UPM transactions.
Figure 10-58
The following events initiate a UPM cycle:
10-72
6. The CPU now commences fetching instructions, in random order, from the FCM buffer RAM. This
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first-level boot loader typically copies a secondary boot loader into system memory, and continues
booting from there. Boot software must clear FMR[BOOT] to enable normal operation of FCM.
Any internal device requests an external memory access to an address space mapped to a
chip-select serviced by the UPM
A UPM refresh timer expires and requests a transaction, such as a DRAM refresh
A bus monitor time-out error during a normal UPM cycle redirects the UPM to execute an
exception sequence
LUPWAIT
User-Programmable Machines (UPMs)
shows the basic operation of each UPM.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
If the LGPL4/LGTA/LFRB/LUPWAIT signal is used as both an input and
an output, a weak pull-up is required. Refer to the hardware specification for
details regarding termination options.
Memory Access Request
Figure 10-58. User-Programmable Machine Functional Block Diagram
(issued in software)
Exception Request
Internal / External
Run Command
Timer Request
UPM Refresh
Request
Logic
Wait
Hold
Generator
WAEN Bit
Index
Array
NOTE
(LAST = 0)
Increment
Index
Index
Internal Controls
Internal
Signals
Latch
RAM Array
Generator
Signals
Timing
Freescale Semiconductor
LGPL n
LBS n
LCS n