MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 721

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
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— 10/100 Mbps SGMII
— 1000 Mbps full-duplex SGMII
TCP/IP off-load
— IP v4 and IP v6 header recognition on receive
— IP v4 header checksum verification and generation
— TCP and UDP checksum verification and generation
— Per-packet configurable off-load
— Recognition of VLAN, stacked-VLAN, 802.2, PPPoE session, MPLS stacks, ARP, and
Quality of service (QoS) support
— Transmission from up to eight queues
— Reception to up to eight physical queues
Interrupt coalescing
— Packet-count-based thresholds for both receive and transmit
— Timer-based thresholds
Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):
— IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or software
— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and
— VLAN insertion and deletion
— Retransmission following a collision
— Support for CRC generation and verification of inbound/outbound packets
— Programmable Ethernet preamble insertion and extraction of up to 7 bytes
MAC address recognition:
— Exact match on primary and virtual 48-bit unicast addresses
ESP/AH IP-Security headers
– Priority-based queue selection
– Modified weighted round-robin queue selection with fair bandwidth allocation
– 64 virtual receive queues overlaid on 8 physical buffer descriptor rings
– Table-oriented queue filing strategy based on 16 header fields or flags
– Frame rejection support for filtering applications
– Filing based on Ethernet, IP, and TCP/UDP properties, including VLAN fields, Ether-type,
programmed PAUSE frame generation and recognition)
IEEE 802.1 virtual local area network (VLAN) tags and priority
– Per-frame VLAN control word or default VLAN for each eTSEC
– Extracted VLAN control word passed to software separately
– Programmable VLAN tag to support metropolitan bridging
– VRRP and HSRP support for seamless router fail-over
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
IP protocol type, IP TOS or differentiated services, IP source and destination addresses,
TCP/UDP port numbers
Enhanced Three-Speed Ethernet Controllers
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