MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 95

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
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— Write-protection capability
— Atomic operation
General-purpose chip-select machine (GPCM)
— Compatible with SRAM, EPROM, NOR Flash EEPROM, FEPROM, and peripherals
— Global (boot) chip-select available at system reset
— Boot chip-select support for 8- and 16-bit devices
— Minimum three-clock access to external devices
— Two byte-write-enable signals (LWE[0:1])
NAND Flash control machine (FCM)
— Compatible with small (512 + 16 bytes) and large (2048 + 64 bytes) page parallel NAND
— Global (boot) chip-select available at system reset, with 4-Kbyte boot block buffer for
— Boot chip-select support for 8-bit devices
— Dual 2-Kbyte/eight 512-byte buffers allow simultaneous data transfer during Flash reads and
— Interrupt-driven block transfer for reads and writes
— Programmable command and data transfer sequences of up to eight steps supported
— Generic command and address registers support proprietary Flash interfaces
— Block write locking to ensure system security and integrity
Three user-programmable machines (UPMs)
— Programmable-array-based machine controls external signal timing with a granularity of up to
— User-specified control-signal patterns run when an internal master requests a single-beat or
— UPM refresh timer runs a user-specified control signal pattern to support refresh
— User-specified control-signal patterns can be initiated by software
— Each UPM can be defined to support DRAM devices with depths of 64, 128, 256, and
— Support for 8- and 16-bit devices
— Page mode support for successive transfers within a burst
— Internal address multiplexing supporting 64-, 128-, 256-, and 512-Kbyte, and 1-, 2-, 4-, 8-, 16-,
Optional monitoring of transfers between local bus internal masters and local bus slaves (local bus
error reporting)
Flash EEPROM
execute-in-place boot loading
programming
one quarter of an external bus clock period
burst read or write access
512 Kbytes, and 1, 2, 4, 8, 16, 32, 64, 128, and 256 Mbytes
32-, 64-, 128-, and 256-Mbyte page banks
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Overview
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