MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 516

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.4.3.3.4
The timing for read data transfers is shown in
enable its output drivers and drive valid read data while LFRE is held low. FCM samples read data on the
rising edge of LFRE, which follows an optional number of wait states. Note that FCM will delay the first
read if a RBW or RSW instruction is issued, in which case LFRB sample timing takes effect (see
Section 10.4.3.3.3, “FCM Ready/Busy
10-68
LCLK
(unused)
LFWE
LFCLE/
LFALE
LFRE
LAD[0:7]
TA
LFCLE
LFWE
LFRB
LFRE
write cycle
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
write data
FCM Read Data Timing
long-latency CW command issue
TRLX = 0:
TRLX = 1:
Notes:
Figure 10-54. FCM Delay Prior to Sampling LFRB State
t
t
t
RP
RHT
WRT
8×(2+SCY) cycles
16×(2+SCY) LCLK cycles
(for TRLX = 0, RST = 0, SCY = 1, CLKDIV = 4*N)
= LFRE pulse time, read period.
= LFRE hold time.
= Write to read turnaround time.
Figure 10-55. FCM Read Data Timing
Timing”).
write-to-read turnaround
Figure
LFRB sample
t
WRT
points
10-55. Upon assertion of LFRE, the Flash device will
NAND FlashFlash busy state
t
t
WS
RC
= Read data cycle time.
= Read wait state time.
read cycle
t
RP
read data
t
t
WS
ready state
RC
FCM continues
following LFRB high
Freescale Semiconductor
t
RHT
sample data