MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 276

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
5.8.2.2
The power management controller event register (PMCER), shown in
PMCI bit that the power management controller has detected a wake-up event, that the system is not in
idle state anymore, and that the device should exit low power state. If PMCMR[PMCIE] is set, the PMC
interrupt request to the PowerPC core is driven. When set, bits 23–30 indicate the sources of various
wake-up events.
Table 5-68
5-68
Offset 0x00B04
Reset
Reset
0–22
Bits
23
24
25
W
W
R
R
16
0
(PME)
Name
GPIO
USB
PCI
—
defines the bit fields of PMCER.
Power Management Controller Event Register (PMCER)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved. Write has no effect, read returns 0.
Wake-up event detected.
0 A wake-up event did not occur from this wake-up source.
1 A wake-up event occurred on GPIO. This wake-up event was caused by an unmasked event of GPIO
Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR is cleared.
Wake-up event detected.
0 A wake-up event did not occur from this wake-up source.
1 A wake-up event occurred. This wake up event was caused by an active state of the PCI_PME input
Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR is cleared.
Wake-up event detected.
0 A wake-up event did not occur from this wake-up source.
1 A wake-up event occurred on USB. This wake-up event was caused by a detection of a non idle state on
Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR is cleared.
module. See
bit is set, the PMC will assert interrupt request to the PowerPC core or external PME to the remote host,
depending on the state of PMCCR1[PME_EN]. This bit can be cleared by writing a 1 to the bit location
(writing zero has no effect).
signal. See
corresponding PMCMR bit is set, the PMC will assert interrupt request to the PowerPC core. This bit can
be cleared by writing a 1 to the bit location (writing zero has no effect).
USB interface. See
PMCMR bit is set, the PMC will assert interrupt request to the PowerPC core or external PME to the
remote host, depending on the state of PMCCR1[PME_EN]. This bit can be cleared by writing a 1 to the
bit location (writing zero has no effect).
—
Figure 5-52. Power Management Controller Event Register
Table
Chapter 21, “General Purpose I/O (GPIO),”
22
13-3,
Chapter 16, “Universal Serial Bus Interface,”
GPIO PCI (PME)
Table 5-68. PMCER Bit Settings
23
“PCI Interface Signals—Detailed Signal Descriptions,”
24
All zeros
All zeros
—
USB
Description
25
eTSEC1 eTSEC2 Timer
26
for more details. If the corresponding PMCMR
Figure
for more details. If the corresponding
27
5-52, indicates with the
28
for more details. If the
Freescale Semiconductor
Int1
29
Access: Read/Write
Int2
30
PMCI
15
31