MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 716

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
14.6.4.7
The master control register (MCR), shown in
provides a means for software to reset the SEC.
Table 14-40
14.6.5
SEC transactions can be snooped by the MPC8313E cache if defined as global. This definition is
programmed in the master control register MCR[GI]. See
more details. Note that SEC transactions are defined as global by default.
14-74
22–23
24–29
0–21
Bits
30
31
Reset
Reset
Field
Field
Addr
Addr
R/W
R/W
Names
Priority
SWR
GIH
—
—
Snooping by Caches
describes the MCR fields.
32
Master Control Register (MCR)
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
Priority on master bus. The setting of these bits determines the transaction priority level the SEC asserts
to the device internal arbiter. The SEC does not dynamically alter its priority level based on system
congestion or SEC utilization, however software may change the SEC priority level in realtime.
00 Lowest priority (default)
01 Next lowest priority
10 Next highest priority
11 Highest priority
Reserved
Global inhibit. Writing 1 to this bit prevents output IPM_SNOOP from being asserted.
0 Permit assertion of IPM_SNOOP, allowing the system cache to snoop bus transactions initiated by the
1 Prevent assertion of IPM_SNOOP, preventing the system cache from snooping
Software reset. Writing 1 to this bit will cause a global software reset. Upon completion of the reset, this
bit will be automatically cleared.
0 Do not reset
1 Global reset
SEC.
39
Figure 14-47. Master Control Register (MCR)
40
Table 14-40. MCR Field Descriptions
—
Figure
47
0x0000_0000
0x0000_0000
0x3_ 1030
0x 3_1034
14-47, controls certain functions in the controller and
R/W
48
R/W
Description
14.6.4.7, “Master Control Register (MCR),”
21
PRIORITY
22
23
55
24
56
Freescale Semiconductor
—
29
GIH SWR
30
31
63
for