MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 736

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15-18
0x2_46CC RUND—Receive undersize packet counter
0x2_46DC RDRP—Receive drop counter
0x2_468C TR511—Transmit and receive 256- to 511-byte frame counter
0x2_469C RBYT—Receive byte counter
0x2_46AC RBCA—Receive broadcast packet counter
0x2_46BC RALN—Receive alignment error counter
0x2_46C0 RFLR—Receive frame length error counter
0x2_46C4 RCDE—Receive code error counter
0x2_46C8 RCSE—Receive carrier sense error counter
0x2_46D0 ROVR—Receive oversize packet counter
0x2_46D4 RFRG—Receive fragments counter
0x2_46D8 RJBR—Receive jabber counter
0x2_46EC TBCA—Transmit broadcast packet counter
0x2_46FC TSCL—Transmit single collision packet counter
0x2_46A0 RPKT—Receive packet counter
0x2_46A4 RFCS—Receive FCS error counter
0x2_46A8 RMCA—Receive multicast packet counter
0x2_46B0 RXCF—Receive control frame packet counter
0x2_46B4 RXPF—Receive PAUSE frame packet counter
0x2_46B8 RXUO—Receive unknown OP code counter
0x2_46E0 TBYT—Transmit byte counter
0x2_46E4 TPKT—Transmit packet counter
0x2_46E8 TMCA—Transmit multicast packet counter
0x2_46F0 TXPF—Transmit PAUSE control frame counter
0x2_46F4 TDFR—Transmit deferral packet counter
0x2_46F8 TEDF—Transmit excessive deferral packet counter
0x2_4690 TR1K—Transmit and receive 512- to 1023-byte frame counter
0x2_4694 TRMAX—Transmit and receive 1024- to 1518-byte frame counter
0x2_4698 TRMGV—Transmit and receive 1519- to 1522-byte good VLAN
0x2_4700 TMCL—Transmit multiple collision packet counter
0x2_4704 TLCL—Transmit late collision packet counter
eTSEC1
Offset
frame count
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 15-4. Module Memory Map (continued)
Name
1
eTSEC Transmit Counters
eTSEC Receive Counters
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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