MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 925

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.7.1.5
SGMII mode initialization sequence is very similar to TBI mode initialization. Additional initialization is
required for the SerDes. An example of SGMII mode initialization sequence is shown in
Freescale Semiconductor
SGMII Interface Support
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
SGMII mode utilizes the internal TBI PHY. The internal TBI PHY only
auto-negotiates at 1 Gbps. However, 10 Mbps and 100 Mbps speeds are
supported in SGMII mode. It is recommended that the external PHY inform
the MAC if the desired link speed is not 1 Gbps. Software can perform MII
management cycles to determine the external PHY link speed and program
ECNTRL and MACCFG2 accordingly.
Table 15-176. RTBI Mode Register Initialization Steps (continued)
RX n /RX n
TX n /TX n
Signals
Table 15-177. SGMII Interface Signal Configuration (4-Wire)
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Frequency [MHz] 1250
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
Initialize (Empty) Transmit Descriptor ring and fill buffers with Data
Sum
Voltage [V] LVDS
SerDes Signals
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
I/O
O
I
Initialize DMACTRL (Optional)
Initialize RBASE0–RBASE7,
Initialize TBASE0–TBASE7,
Initialize RCTRL (Optional)
Enable Transmit Queues
Enable Receive Queues
Signals
Enable Rx and Tx,
Initialize RQUEUE
No. of
Initialize TQUEUE
2
2
4
NOTE
Signals
RXD
TXD
Frequency [MHz] 1250
Sum
Voltage [V] LVDS
SGMII Interface
Enhanced Three-Speed Ethernet Controllers
I/O
O
I
Signals
No. of
2
2
4
Table
15-178.
15-207