MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1174

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Revision History
15.5.3.1.6, 15-32
15.5.3.3.1, 15-49
15.5.3.3.7, 15-57
15.5.3.3.8, 15-58
15.5.3.5.1, 15-67
15.5.3.5.2, 15-67
A-16
25–26
27
0
28
GPI
FGPIEN
R100M
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
General purpose interrupt. When a property matches the value in the RQPROP entry at this index, and
REJ = 0 and AND = 0, the filer will instruct the Rx descriptor controller to set IEVENT[FGPI] when the
corresponding receive frame is written to memory.
If the timer is enabled (TMR_CTRL[TE] = 1), then TMR_PEVENT[RXP] will also be set.
RGMII 100 mode. This bit is ignored unless RPM are set and MACCFG2[I/F Mode] is assigned to
10/100 (01).
0 RGMII is in 10 Mbps mode;
1 RGMII is in 100 Mbps mode;
Reserved
Filer general purpose interrupt enable
In Table 15-10, changed the description in bit 28 to the following:
In Table 15-27, bit 29, in the Description column, added the following sentence:
Note that frames less than or equal to 16B in length are always silently dropped.
In Figure 15-29, changed bit 0 to GPI and the reset value to ‘undefined’.
In Table 15-33, add the following for bit 0, GPI:
In Figure 5-29, changed the reset value to ‘undefined’.
In Table 15-34, bits 16-31, in the Description column, replaced the fourth
paragraph with the following:
A value in the length/type field greater than 1500 and less than 1536 is treated as a type encoding
by the parser. Since no recognized types exist in this range, the controller will not parse beyond the
length/type field of any such frame.
Replaced item 4 and added the following text:
4. The MPLS tagged packets—In this case, one can use arbitrary extraction bytes to compare to
Note: Users of the eTSEC parser/filer should be aware of a difference in behavior between rev 1
In Table 15-39, bits 26 and 27, add the following statement in the Description
column after the first paragraph: Must be 0 if MACCFG2[Full Duplex] = 0.
In Table 15-40, bits 16–19, in the Description column, added the following
sentence: ‘Values from 0x3 to 0xF are supported by the controller.’
For bit 29, in the Description column, changed the first paragraph to read:
Pad and append CRC. This bit is cleared by default. This bit must be set when in half-duplex mode
(MACCFG2[Full Duplex] is cleared).
the actual ethertype if a filer rule is intending to file based on an MPLS label existence.
and rev 2 silicon in cases where the Ethernet type/length field contains a value between
1500 and 1536.
In rev 2 silicon, values between 1500 and 1536 are interpreted as a type. Since there are
currently no valid types in this range publicly defined by IANA, the controller will not parse
beyond the length/type field of any such frame.
If the same packet is encountered with rev 1 silicon, parser/filer behavior is different. With
rev 1 silicon, such packets are treated as payload length. S/W must confirm the parser and
filer results by checking the type/length field after the packet has been written to memory to
see if it falls in this range.
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