MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 424

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DDR Memory Controller
Read and write accesses to memory are burst oriented; accesses start at a selected location and continue
for a programmed number of higher locations (4 or 8) in a programmed sequence. Accesses to closed pages
start with the registration of an ACTIVE command followed by a READ or WRITE. (Accessing open
pages does not require an ACTIVE command.) The address bits registered coincident with the activate
command specifies the logical bank and row to be accessed. The address coincident with the READ or
WRITE command specify the logical bank and starting column for the burst access.
The data interface is source synchronous, meaning whatever sources the data also provides a clocking
signal to synchronize data reception. These bidirectional data strobes (MDQS[0:3]) are inputs to the
controller during reads and outputs during writes. The DDR SDRAM specification requires the data strobe
signals to be centered within the data tenure during writes and to be offset by the controller to the center
of the data tenure during reads. This delay is implemented in the controller for both reads and writes.
The address and command interface is also source synchronous, although 1/4 cycle adjustments are
provided for adjusting the clock alignment.
9-30
Request from
Address from
Data from
Data from
CSB
SDRAM
Master
Master
Master
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
DQ
Address
Decode
Figure 9-19. DDR Memory Controller Block Diagram
Open
Table
Row
Delay Chain
DQ
FIFO
POS
FIFO
NEG
Address
SDRAM
Control
Control
SDRAM
Control
EN
EN
Freescale Semiconductor
DDR SDRAM
Memory Array
DDR SDRAM
Memory Control
Data Strobes
Data Signals
Clocks
Debug Signals
MA[14:0]
MCS[0:1]
MBA[2:0]
MSRCID[0:4]
MDVAL
MCAS
MRAS
MWE
MDM[0:3]
MCKE
MODT[0:1]
MDQS[0:3]
MDQ[0:31]
MCK
MCK