MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 805

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.5.3.6.16 Receive Alignment Error Counter (RALN)
Figure 15-67
Table 15-71
15.5.3.6.17 Receive Frame Length Error Counter (RFLR)
Figure 15-68
Table 15-72
Freescale Semiconductor
16–31
16–31
0–15
Bits
0–15
Bits
Offset eTSEC1:0x2_46BC; eTSEC2:0x2_56BC
Reset
Offset eTSEC1:0x2_46C0; eTSEC2:0x2_56C0
Reset
W
W
R
R
Name
RFLR
Name
RALN
0
0
—
—
describes the fields of the RALN register.
describes the fields of the RFLR register.
describes the definition for the RALN register.
describes the definition for the RFLR register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
Receive frame length error counter. Increments for each frame received in which the 802.3 length field did
not match the number of data bytes actually received (46–1500 bytes). The counter does not increment if
the length field is not a valid 802.3 length, such as an Ethertype value.
Reserved
(VLAN) which contains an invalid FCS and is not an integral number of bytes.
Receive alignment error counter. Increments for each received frame from 64 to 1518 (non VLAN) or 1522
Figure 15-68. Receive Frame Length Error Counter Register Definition
Figure 15-67. Receive Alignment Error Counter Register Definition
—
—
Table 15-71. RALN Field Descriptions
Table 15-72. RFLR Field Descriptions
All zeros
All zeros
15 16
15 16
Description
Description
Enhanced Three-Speed Ethernet Controllers
RALN
RFLR
Access: Read/Write
Access: Read/Write
15-87
31
31