MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1062

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
given endpoint and the given direction. In a functional stall condition, the device controller will continue
to return STALL responses to all transactions occurring on the respective endpoint and direction until the
endpoint stall bit is cleared by the DCD.
A protocol stall, unlike a function stall, is used on control endpoints is automatically cleared by the device
controller at the start of a new control transaction (setup phase). When enabling a protocol stall, the DCD
should enable the stall bits (both directions) as a pair. A single write to the ENDPTCTRLn register can
ensure that both stall bits are set at the same instant.
16.8.3.2
Data toggle is a mechanism to maintain data coherency between host and device for any given data pipe.
For more information on data toggle, refer to the Universal Serial Bus Revision 2.0 Specification.
16.8.3.2.1
The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device
controller by writing a '1' to the data toggle reset bit in the ENDPTCTRLn register. This should only be
necessary when configuring/initializing an endpoint or returning from a STALL condition.
16.8.3.2.2
This feature is for test purposes only and should never be used during normal device controller operation.
Setting the data toggle Inhibit bit active ('1') causes the USB_DR to ignore the data toggle pattern that is
normally sent and accept all incoming data packets regardless of the data toggle state.
In normal operation, the USB_DR checks the DATA0/DATA1 bit against the data toggle to determine if
the packet is valid. If Data PID does not match the data toggle state bit maintained by the device controller
for that endpoint, the Data toggle is considered not valid. If the data toggle is not valid, the device
controller assumes the packet was already received and discards the packet (not reporting it to the DCD).
16-134
SETUP packet received by a non-control endpoint
IN/OUT/PING packet received by a non-control endpoint
IN/OUT/PING packet received by a non-control endpoint
SETUP packet received by a control endpoint
IN/OUT/PING packet received by a control endpoint
IN/OUT/PING packet received by a control endpoint
Data Toggle
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Any write to the ENDPTCTRLn register during operational mode must
preserve the endpoint type field (that is, perform a read-modify-write).
Data Toggle Reset
Data Toggle Inhibit
Table 16-85. Device Controller Stall Response Matrix
USB Packet
NOTE
Endpoint
Stall Bit.
N/A
N/A
'1
'0
'1
'0
STALL Bit.
Effect on
Cleared
None
None
None
None
None
ACK/NAK/NYET
ACK/NAK/NYET
Freescale Semiconductor
USB Response
STALL
STALL
STALL
ACK