MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 338

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

e300 Processor Core Overview
The following supervisor-level SPRs are implementation-specific (not defined in the PowerPC
architecture):
Table 7-2
7-20
Bits
0
1
•
•
•
•
•
•
•
•
•
•
•
•
DMISS and IMISS are read-only registers that are loaded automatically on an instruction or data
TLB miss.
HASH1 and HASH2 contain the physical addresses of the primary and secondary page table entry
groups (PTEGs).
ICMP and DCMP contain a duplicate of the first word in the page table entry (PTE) for which the
table search is looking.
The required physical address (RPA) register is loaded by the core with the second word of the
correct PTE during a page table search.
The system version register (SVR) is available on the e300 core, which identifies the specific
version (model) and revision level of the system-on-a-chip (SOC) integration.
System memory base address (MBAR) is an implementation-specific register available on the
e300 core. It supports a temporary storage for the system-level memory map.
The instruction and data address breakpoint registers (IABR, IABR2, DABR, DABR2) are loaded
with an instruction or data address, respectively, that is compared to instruction addresses in the
dispatch queue or to the data address in the LSU. When an address match occurs, a breakpoint
interrupt is generated.
One instruction breakpoint control register (IBCR) and one data breakpoint control register
(DBCR) are implemented in the e300 core.
To support critical interrupts, two registers (CSRR0 and CSRR1) are included in the e300 core.
Eight SPRG registers (SPRG0–SPRG7) are in the e300 core.
Block address translation (BAT) arrays—The e300 core has eight instruction and eight data BAT
registers.
The hardware implementation (HID0 and HID1) registers provide the means for enabling core
checkstops and features and allow software to read the configuration of the PLL configuration
signals. The HID2 register enables the true little-endian mode, cache way-locking, and the
additional BAT registers.
shows the bit definitions for HID0.
EMCP
Name
ECPE
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Enable mcp . The purpose of this bit is to mask out machine check interrupts caused by assertion of
mcp , similar to how MSR[EE] can mask external interrupts.
0 Masks mcp . Asserting mcp does not generate a machine check interrupt or a checkstop.
1 Asserting mcp causes checkstop if MSR[ME] = 0 or a machine check interrupt if ME = 1
Enable cache parity errors.
0 Disables instruction and data cache parity error reporting
1 Allows a detected cache parity error to cause a machine check interrupt if MSR[ME] = 1 or a
checkstop if MSR[ME] = 0
Table 7-2. e300 HID0 Bit Descriptions
Function
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