MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1093

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

17.3.1.5
The I2Cn data register is shown in
Table 17-8
17.3.1.6
I2CnDFSRR is shown in
Freescale Semiconductor
Bits
Bits
0–7
6
7
Name
DATA
Name
RXAK
MIF
shows the bit descriptions for I2CnDR.
Offset 0x0_3010
Offset 0x0_3014
Reset
Reset
I
Digital Filter Sampling Rate Register (I2C n DFSRR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
C n Data Register (I2C n DR)
Transmission starts when an address and the R/W bit are written to the data register and the I
performs as the master. A data transfer is initiated when data is written to the I2C n DR. The most-significant
bit is sent first in both cases. In master receive mode, reading the data register allows the read to occur, but
also allows the I
function is available after it is addressed. Note that in both master receive and slave receive modes, the very
first read is always a dummy read.
W
W
R
R
Module interrupt. The MIF bit is set when an interrupt is pending, causing a processor interrupt request
(provided I2C n CR[MIEN] is set).
0 No interrupt is pending. Can be cleared only by software.
1 Interrupt is pending. MIF is set when one of the following events occurs:
Received acknowledge. The value of SDA n during the reception of acknowledge bit of a bus cycle. If the
received acknowledge bit (RXAK) is low, it indicates that an acknowledge signal has been received after
the completion of eight bits of data transmission on the bus. If RXAK is high, it means no acknowledge
signal has been detected at the 9th clock.
0 Acknowledge received
1 No acknowledge received
Figure 17-7. I
• One byte of data is transferred (set at the falling edge of the 9th clock).
• The value in I2C n ADR matches with the calling address in slave-receive mode.
• Arbitration is lost.
0
0
0
Figure
—
Table 17-7. I2C n SR Field Descriptions (continued)
2
C module to receive the next byte of data on the I
0
1
2
Figure 17-6. I
17-7.
C n Digital Filter Sampling Rate Register (I2C n DFSRR)
Table 17-8. I2C n DR Field Descriptions
Figure
0
2
17-6.
2
C n Data Register (I2C n DR)
1
All zeros
DATA
Description
Description
0
DFSR
0
2
C interface. In slave mode, the same
Access: Read/write
Access: Read/write
0
0
7
7
2
C interface
I
2
C Interfaces
17-9