MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 374

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Integrated Programmable Interrupt Controller (IPIC)
Table 8-13
Figure 8-9
Table 8-14
8.5.7
SICNR, shown in
SYSA0–SYSA1 and SYSD0–SYSD1 priority positions. All other priority positions assert int to the core.
8-16
0–31
Offset 0x24
Reset
Bits Name
0–31
Bits Name
W
R
INT n Each implemented bit (listed in
INT n Each implemented bit (listed in
0
shows SIMSR_L.
defines the bit fields of SIMSR_H.
defines the bit fields of SIMSR_L.
System Internal Interrupt Control Register (SICNR)
interrupt by clearing the corresponding SIMSR bit. An interrupt is unmasked (enabled) by setting the
corresponding SIMSR bit. The SIMSR can be read by the user at any time.
Note:
Unimplemented bits, shown as reserved in
interrupt by clearing the corresponding SIMSR bit. An interrupt is unmasked (enable) by setting the
corresponding SIMSR bit. The SIMSR can be read by the user at any time.
Note:
Unimplemented bits, shown as reserved in
• SIMSR bit positions are not changed according to their relative priority.
• The user can clear pending register bits that were set by multiple interrupt events only by clearing all unmasked
• If an SIMSR bit is masked at the same time that the corresponding SIPNR bit causes an interrupt request to
• SIMSR bit positions do not change according to their relative priority.
• The user can clear pending register bits that were set by multiple interrupt events only by clearing all
• If an SIMSR bit is masked at the same time that the corresponding SIPNR bit causes an interrupt request to
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
events in the corresponding event register.
the core, the error vector is issued (if no other interrupts are pending). Thus, the user should always include
an error
unmasked events in the corresponding event register.
the core, the error vector is issued (if no other interrupts are pending). Thus, the user should always include
an error vector routine, even if it contains only an rfi instruction. The error vector cannot be masked.
Figure
Figure 8-9. System Internal Interrupt Mask Register (SIMSR_L)
8-10, defines the IPIC output interrupt type (int, cint, or smi) in the
Table 8-13. SIMSR_H Field Descriptions
Table 8-14. SIMSR_L Field Descriptions
INT n (Implemented bits are listed in
Table
Table
8-9) corresponds to an external interrupt source. The user masks an
8-7) corresponds to an external interrupt source. The user masks an
Figure
Table
All zeros
Description
Description
8-7, are ignored on writes; read = 0.
8-9, are ignored on writes; read = 0.
Table
8-9.)
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Access: Read/write
31