MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 285

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

The relationship between the e300 core and the defined PMC power states is illustrated in
Freescale Semiconductor
(PMCCR[SL
PEN]=0)
System
Full On
Mode
•
Generating or responding to appropriate control signals relative to low power modes: VDD
switching control (EXT_PWR_CTRL) output signal and input signal indicating external power is
stable (PMC_PWR_OK)
Mode
Sleep
Doze
Core
Nap
Full
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
On
The relationships shown below between e300 core doze, nap, and sleep
modes and PCI D-states are only suggested. There is no forced hardware
relationship between these states. For example, if a PCI host sets
PCIPMR1[Power_State] = 01, it is still up to the software running on the
e300 to put itself into doze mode.
Table 5-74. Software-Controller Power-Down States—Basic Description
PCI D- state
PCIPMR1[P
owerState]=
PCIPMR1[P
owerState]=
PCIPMR1[P
owerState]=
PCIPMR1[P
owerState]=
Suggested
D0
D1
D2
D2
00
01
10
10
All units operating normally
Core stops dispatching new instructions
(core is halted), and most of the core
functional units are disabled. System
operates normally.
Core is stopped with its clocks off except to
time base. System operates normally.
Core is stopped with its clocks off. Core
clocks powered down to all blocks (including
core time base) except to the
interrupt unit. System operates normally.
Description
NOTE
Snoop Interrupt
Core Responds
Yes
Yes
No
No
to
Yes
Yes
Yes
Yes
strl state
SDRAM
Active
Active
Active
Active
DDR
System Configuration
Table
Quiesce
Negated
Negated
Negated
Negated
5-74.
Signal
State
5-77