MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 403

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

1
9.4.1
This section describes the DDR memory controller registers. Shading indicates reserved fields that should
not be written.
9.4.1.1
The chip select bounds registers (CSn_BNDS) define the starting and ending address of the memory space
that corresponds to the individual chip selects. Note that the size specified in CSn_BNDS should equal the
size of physical DRAM. Also, note that EAn must be greater than or equal to SAn.
If chip select interleaving is enabled, all fields in the lower interleaved chip select are used, and the other
chip selects’ bounds registers are unused. For example, if chip selects 0 and 1 are interleaved, all fields in
CS0_BNDS are used, and all fields in CS1_BNDS are unused.
CSn_BNDS are shown in
Freescale Semiconductor
Offset 0x000, 0x008
Reset
0x140–
0x150–
0xBFC
Offset
0x11C
0xBF4
0xBF8
0x110
0x114
0x118
0x120
0x124
0x128
0x130
0x144
0x148
Implementation-dependent reset values are listed in specified section/page.
W
R
0
DDR_SDRAM_CFG—DDR SDRAM control configuration
DDR_SDRAM_CFG_2—DDR SDRAM control configuration 2
DDR_SDRAM_MODE—DDR SDRAM mode configuration
DDR_SDRAM_MODE_2—DDR SDRAM mode configuration 2
DDR_SDRAM_MD_CNTL—DDR SDRAM mode control
DDR_SDRAM_INTERVAL—DDR SDRAM interval configuration
DDR_DATA_INIT—DDR SDRAM data initialization
DDR_SDRAM_CLK_CNTL—DDR SDRAM clock control
Reserved
DDR_INIT_ADDR—DDR training initialization address
Reserved
DDR_IP_REV1—DDR IP block revision 1
DDR_IP_REV2—DDR IP block revision 2
Register Descriptions
Chip Select Memory Bounds (CS n _BNDS)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
Table 9-5. DDR Memory Controller Memory Map (continued)
Figure 9-2. Chip Select Bounds Registers (CS n _BNDS)
Figure
7
8
9-2.
Register
SA n
All zeros
15 16
—
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
R
R
23 24
0x nnnn _ nnnn
0x00 nn _00 nn
0x0000_0000
0x0000_0000
0x0000_0000
0x0200_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0200_0000
Reset
—
—
DDR Memory Controller
Access: Read/Write
1
1
EA n
Section/Page
9.4.1.10/9-23
9.4.1.11/9-24
9.4.1.12/9-26
9.4.1.13/9-27
9.4.1.14/9-27
9.4.1.15/9-28
9.4.1.16/9-28
9.4.1.17/9-29
9.4.1.7/9-18
9.4.1.8/9-21
9.4.1.9/9-22
—
—
9-9
31