MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 410

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DDR Memory Controller
9.4.1.6
DDR SDRAM timing configuration 2, shown in
9-16
Offset 0x10C
16–19
21–23
25–27 ACTTOACT Activate-to-activate interval (t
29–31 WRTORD Last write data pair to read command issue interval (t
Reset
Bits
20
24
28
W
R
—
0
REFREC
WRREC
Name
—
—
—
ADD_LAT
1
DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 9-7. DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2)
Refresh recovery time (t
command is allowed. This field is concatenated with TIMING_CFG_3[EXTREFREC] to obtain a 7-bit value
for the total refresh recovery. Note that hardware adds an additional 8 clock cycles to the final, 7-bit value
of the refresh recovery, such that t
0000 8 clocks
0001 9 clocks
0010 10 clocks
Reserved, should be cleared.
Last data to precharge minimum interval (t
associated with a write command until a precharge command is allowed.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
Reserved, should be cleared.
activate command is allowed for a different logical bank in the same physical bank (chip select).
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
Reserved, should be cleared.
data pair and the subsequent read command to the same physical bank.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
3 4
CPO
Table 9-10. TIMING_CFG_1 Field Descriptions (continued)
8 9 10
— WR_LAT
RFC
12 13
). Controls the number of clock cycles from a refresh command until an activate
RRD
0011 11 clocks
…
1111 23 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
—
). Number of clock cycles from an activate command until another
RFC
15 16
Figure
is calculated as follows: t
RD_TO_PRE WR_DATA_DELAY — CKE_PLS
All zeros
WR
). Determines the number of clock cycles from the last data
Description
9-7, sets the clock delay to data for writes.
18
WTR
19
). Number of clock cycles between the last write
RFC
= {EXT_REFREC || REFREC} + 8.
21 22 23
Freescale Semiconductor
Access: Read/Write
25 26
FOUR_ACT
31