MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 729

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.5
The eTSECs use a software model that is a superset of the PowerQUICC II Pro TSEC functionality and is
similar to that employed by the Fast Ethernet function supported on the Freescale MPC8260 CPM FCC
and in the FEC of the MPC860T.
The eTSEC device is programmed by a combination of control/status registers (CSRs) and buffer
descriptors. The CSRs are used for mode control, interrupts, and to extract status information. The
descriptors are used to pass data buffers and related buffer status or frame information between the
hardware and software.
All accesses to and from the registers must be made as 32-bit accesses. There is no support for accesses of
sizes other than 32 bits. Writes to reserved register bits must always store 0, as writing 1 to reserved bits
may have unintended side-effects. Reads from unmapped register addresses return zero. Unless otherwise
specified, the read value of reserved bits in mapped registers is not defined, and must not be assumed to
be 0.
This section of the document defines the memory map and describes the registers in detail. The buffer
descriptor is described in
15.5.1
Each of the eTSECs is allocated 4 Kbytes of memory-mapped space. The space for each eTSEC is divided
as indicated in
Freescale Semiconductor
TSEC_1588_ALARM1
TSEC_1588_ALARM2
Signal
Memory Map/Register Definition
Top-Level Module Memory Map
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table
Table 15-2. eTSEC Signals—Detailed Signal Descriptions (continued)
15-3.
I/O
O
O
1588 timer alarm 1. Timer current time is equal to or greater than alarm time comparator register.
User reprograms the TSEC_1588_ALARMn_H/L register to deactivate this output (chip external
output pin)
1588 timer alarm 2. Timer current time is equal to or greater than alarm time comparator register.
User reprograms the 1588_ALARMn_H/L register to deactivate this output (chip external output
pin)
Section 15.6.7, “Buffer Descriptors.”
Address Offset
A00–AFF
B00–BFF
000–0FF
100–2FF
300–4FF
500–5FF
600–7FF
800–8FF
900–9FF
Table 15-3. Module Memory Map Summary
eTSEC general control/status registers
eTSEC transmit control/status registers
eTSEC receive control/status registers
MAC registers
RMON MIB registers
Hash table registers
FIFO control/status registers
DMA system registers
Function
—
Description
Enhanced Three-Speed Ethernet Controllers
15-11