MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1075

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Notice that the device controller handles all errors on Bulk/Control/Interrupt Endpoints except for a data
buffer overflow. However, for ISO endpoints, errors packets are not retried and errors are tagged as
indicated.
16.8.6
The interrupt service routine must consider that there are high-frequency, low-frequency operations, and
error operations and order accordingly.
16.8.6.1
High frequency interrupts in particular should be handed in the order below. The most important of these
is listed first because the DCD must acknowledge a setup buffer in the timeliest manner possible.
1
16.8.6.2
The low frequency events include the following interrupts. These interrupt can be handled in any order
since they don’t occur often in comparison to the high-frequency interrupts.
Freescale Semiconductor
Overflow
ISO Packet
Error
ISO Fulfillment
Error
Execution
It is likely that multiple interrupts to stack up on any call to the Interrupt Service Routine AND during the Interrupt Service
Routine.
Order
1a
1b
2
USB Interrupt
ENDPTSETUPSTATUS
USB Interrupt
ENDPTCOMPLETE
SOF Interrupt
Servicing Interrupts
High-Frequency Interrupts
Low-Frequency Interrupts
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Number of bytes received exceeded max. packet size or total buffer length.
** This error will also set the Halt bit in the dQH and if there are dTDs remaining in the linked list for the
endpoint, then those will not be executed.
CRC Error on received ISO packet. Contents not guaranteed to be correct.
Host failed to complete the number of packets defined in the dQH mult field within the given (micro)frame. For
scheduled data delivery the DCD may need to readjust the data queue because a fulfillment error will cause
Device Controller to cease data transfers on the pipe for one (micro)frame. During the ‘dead’ (micro)frame,
the Device Controller reports error on the pipe and primes for the following frame.
Interrupt
1
Copy contents of setup buffer and acknowledge setup packet (as indicated in section
Managing Queue Heads). Process setup packet according to USB 2.0 Chapter 9 or
application specific protocol.
Handle completion of dTD as indicated in section Managing Queue Heads.
Action as deemed necessary by application. This interrupt may not have a use in all
applications.
Table 16-93. Interrupt Handling Order
Table 16-92. Error Descriptions
Action
Universal Serial Bus Interface
16-147