MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 948

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
Note that this register is shared between the host and device mode functions. In host mode, it is the
PERIODICLISTBASE register; in device mode, it is the DEVICEADDR register. See
“Device Address Register (DEVICEADDR)—Non-EHCI,”
16.3.2.7
This register is not defined in the EHCI specification. In device mode, the upper seven bits of this register
represent the device address. After any controller reset or a USB reset, the device address is set to the
default address (0). The default address will match all incoming addresses. Software shall reprogram the
address after receiving a SET_ADDRESS descriptor.
Note that this register is shared between the host and device mode functions. In device mode, it is the
DEVICEADDR register; in host mode, it is the PERIODICLISTBASE register. See
“Periodic Frame List Base Address Register (PERIODICLISTBASE),”
16.3.2.8
This 32-bit register contains the address of the next asynchronous queue head to be executed by the host.
Bits 4–0 of this register cannot be modified by the system software and always return zeros when read.
16-20
31–12
31–25
11–0
24–0
Offset 0x2_3154
Reset n
Offset 0x2_3154
Reset
Bits
Bits
W
W
R
R
31
31
USBADR
PERBASE
Name
Name
n n n n
—
—
Device Address Register (DEVICEADDR)—Non-EHCI
Current Asynchronous List Address Register (ASYNCLISTADDR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
USBADR
Figure 16-12. Periodic Frame List Base Address (PERIODICLISTBASE)
Device address. This field corresponds to the USB device address.
Reserved, should be cleared.
Reserved, should be cleared.
Base address. Correspond to memory address signal [31:12]. Only used in the host mode.
Table 16-15. PERIODICLISTBASE Register Field Descriptions
n n n n n
Table 16-16. DEVICEADDR Register Field Descriptions
25 24
Figure 16-13. Device Address (DEVICEADDR)
PERBASE
n n n n
n n 0 0 0
All zeros
Description
Description
for more information.
12 11
0
—
0
0
for more information.
0
0
0
0
Freescale Semiconductor
Section 16.3.2.6,
—
0
Access: Read/Write
Access: Read/Write
Section 16.3.2.7,
0
0
0
0
0
0
0