MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 420

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DDR Memory Controller
9.4.1.12
The DDR SDRAM interval configuration register, shown in
cycles between bank refreshes issued to the DDR SDRAMs. In addition, the number of DRAM cycles that
a page is maintained after it is accessed is provided here.
Table 9-18
9-26
16–17
18–31 BSTOPRE Precharge interval. Sets the duration (in memory bus clocks) that a page is retained after a DDR SDRAM
0–15
Bits
Offset 0x124
Reset
MD_VALUE
CKE_CNTL
MD_SEL
CS_SEL
W
Field
R
REFINT
Name
—
0
Figure 9-13. DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL)
describes the DDR_SDRAM_INTERVAL fields.
DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Refresh interval. Represents the number of memory bus clock cycles between refresh cycles. Depending on
DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each DDR SDRAM physical bank
during each refresh cycle. The value for REFINT depends on the specific SDRAMs used and the interface
clock frequency. Refreshes are not issued when the REFINT is set to all 0s.
Reserved
access. If BSTOPRE is zero, the DDR memory controller uses auto-precharge read and write commands
rather than operating in page mode. This is called global auto-precharge mode.
Select mode register.
See
Value written to mode
register
Mode Register Set
Table 9-17. Settings of DDR_SDRAM_MD_CNTL Fields (continued)
Table 9-16
Table 9-18. DDR_SDRAM_INTERVAL Field Descriptions
0
.
REFINT
Chooses chip select (CS)
Refresh
—
—
0
All zeros
Description
15 16 17 18
Only bit five is significant.
See
Selects logical bank
Figure
—
Table 9-16
Precharge
0
9-13, sets the number of DRAM clock
.
BSTOPRE
See
Clock Enable Signals
Table 9-16
Freescale Semiconductor
Access: Read/Write
Control
—
—
—
.
31