MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1043

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.6.12.3.6 Complete-Split for Scheduling Boundary Cases 2a, 2b
Boundary cases 2a and 2b (INs only) (see
state context of the previous siTD to finish the split transaction.
state fields.
If software has budgeted the schedule of this data stream with a frame wrap case, then it must initialize the
siTD[Back Pointer] field to reference a valid siTD and have the T bit in the siTD[Back Pointer] field
cleared. Otherwise, software must set the T bit in siTD[Back Pointer]. The host controller's rules for
interpreting when to use the siTD[Back Pointer] field are listed below. These rules apply only when the
siTD's Active bit is a one and the SplitXState is Do Complete Split.
When either of these conditions apply, then the host controller must use the transaction state from siTD
In order to access siTD
Pointer].
The host controller must save the entire state from siTD
accommodate for case 2b processing. The host controller must not recursively walk the list of siTD[Back
Pointers].
If siTD
applied as described above. If these criteria to execute a complete-split are met, the host controller executes
the complete split and evaluates the results as described above. The transaction state (see
siTD
of siTD
next pointer to the next schedule item. No updates to siTD
If siTD
the Active bit and set the Missed Micro-Frame status bit and the resultant status is written back to memory.
If siTD
siTD
complete-split transaction cleared it), then the host controller returns to the context of siTD
transitions its SplitXState to Do Start Split. The host controller then determines whether the case 2b start
split boundary condition exists (that is, if cMicroframeBit is 1 and siTD
Freescale Semiconductor
•
•
X-1
X
's back pointer, it transitioned to zero as a result of a detected error, or the results of siTD
X-1
X-1
X-1
When cMicroFrameBit is a 0x1 and the siTD
If cMicroFrameBit is a 0x2 and siTDX[S-mask[0]] is zero
X-1
is appropriately advanced based on the results and written back to memory. If the resultant state
's Active bit is cleared, (because it was cleared when the host controller first visited siTD
is active (Active bit is set and SplitXStat is Do Complete Split), then both Test A and Test B are
's Active bit is a one, then the host controller returns to the context of siTD
is active (Active bit is set and SplitXStat is Do Start Split), then the host controller must clear
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
TP and T-count are used only for Host to Device (OUT) endpoints.
Total Bytes To Transfer
P (page select)
Current Offset
TP (transaction position)
T-count (transaction count)
X-1
Buffer State
, the host controller reads on-chip the siTD referenced from siTD
Table 16-71. Summary siTD Split Transaction State
Figure
All bits in the status field
16-57) require that the host controller use the transaction
NOTE
Status
X
[Back Pointer] T-bit is zero, or
X
while processing siTD
X
are necessary.
Table 16-71
C-prog-mask
Execution Progress
X
[S-mask[0]] is 1). If this criterion
enumerates the transaction
X-1
Universal Serial Bus Interface
. This is to
X
, and follows its
Table
X
X
[Back
and
16-71) of
X-1
X-1
's
16-115
X-1
via
.