MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1069

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

The transaction error bit set in the status field indicates a fulfillment error condition. When a fulfillment
error occurs, the frame after the transfer failed to complete wholly, the device controller will force retire
the ISO-dTD and move to the next ISO-dTD.
It is important to note that fulfillment errors are only caused due to partially completed packets. If no
activity occurs to a primed ISO-dTD, the transaction will stay primed indefinitely. This means it is up to
software discard transmit ISO-dTDs that pile up from a failure of the host to move the data.
Finally, the last difference with ISO packets is in the data level error handling. When a CRC error occurs
on a received packet, the packet is not retried similar to bulk and control endpoints. Instead, the CRC is
noted by setting the Transaction Error bit and the data is stored as usual for the application software to sort
out.
16.8.3.6.1
When it is necessary to synchronize an isochronous data pipe to the host, the (micro)frame number
(FRINDEX register) can be used as a marker. To cause a packet transfer to occur at a specific (micro)frame
number [N], the DCD should interrupt on SOF during frame N-1. When the FRINDEX=N-1, the DCD
must write the prime bit. The USB_DR will prime the isochronous endpoint in (micro)frame N-1 so that
the device controller will execute delivery during (micro)frame N.
Freescale Semiconductor
•
•
TX Packet Retired
— MULT counter reaches zero.
— Fulfillment Error [Transaction Error bit is set]
— #Packets Occurred > 0 AND # Packets Occurred < MULT
RX Packet Retired:
— MULT counter reaches zero.
— Non-MDATA Data PID is received
— Overflow Error:
— Packet received is > maximum packet length. [Buffer Error bit is set]
— Packet received exceeds total bytes allocated in dTD. [Buffer Error bit is set]
— Fulfillment Error [Transaction Error bit is set]
— # Packets Occurred > 0 AND # Packets Occurred < MULT
— CRC Error [Transaction Error bit is set]
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
For TX-ISO, MULT Counter can be loaded with a lesser value in the dTD
Multiplier Override field. If the Multiplier Override is zero, the MULT
Counter is initialized to the Multiplier in the QH.
For ISO, when a dTD is retired, the next dTD is primed for the next frame.
For continuous (micro)frame to (micro)frame operation the DCD should
ensure that the dTD linked-list is out ahead of the device controller by at
least two (micro)frames.
Isochronous Pipe Synchronization
NOTE
NOTE
Universal Serial Bus Interface
16-141