MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 177

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

4.3.1.2
When the device is configured as a PCI host, the CFG_CLKIN_DIV configuration input selects the
relationship between SYS_CLK_IN and PCI_SYNC_OUT as shown in
device supports threeoutput signals. The frequency of the output clocks will be equal to the
PCI_SYNC_OUT frequency.
When the device is configured as a PCI agent, the CFG_CLKIN_DIV configuration input can be used to
double the internal clock frequencies, if sampled as ‘0’ during power-on reset assertion. This feature is
useful if a fixed internal frequency is desired regardless of whether the PCI clock is running at 33 or
66 MHz. PCI specifications require the PCI clock frequency information to be provided by the M66EN
signal.
When the device is configured as PCI host, there are two scenarios for connecting the CFG_CLKIN_DIV
configuration input. If the frequency of SYS_CLK_IN is 33 MHz (that is, the PCI system is running on a
33-MHz clock), CFG_CLKIN_DIV should be connected high. If the frequency of SYS_CLK_IN is
66 MHz (that is, the PCI system can run at 33- or 66-MHz clock signaled by M66EN), CFG_CLKIN_DIV
should be connected to the M66EN signal.
4.3.1.3
The example described in
input signals (CFG_RESET_SOURCE, CFG_CLKIN_DIV). The reset sequence duration is measured
from the negation of PORESET to the negation of HRESET. Note that the duration mentioned in this table
is typical and does not represent cases in which the process of loading the reset configuration word had to
be retried due to errors.
Freescale Semiconductor
Configuration
I
2
C EEPROM
Words
No
No
CFG_CLKIN_DIV
1
0
SYS_CLK_IN Division
Selecting Reset Configuration Input Signals
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
SYS_CLK_IN
(Host Mode)
Frequency
33 MHz
66 MHz
In PCI host mode, SYS_CLK_IN: PCI_SYNC_OUT = 1:1 and all PCI_CLK_OUT[0:2] clocks
are running at a frequency which is equal to the SYS_CLK_IN frequency
In PCI agent mode, SYS_CLK_IN: PCI_SYNC_OUT = 2:1 and all PCI_CLK_OUT[0:2] clocks
are running at a frequency which is equal to the PCI_SYNC_OUT frequency.
Table 4-7
Table 4-7. Selecting Reset Configuration Input Signals
CFG_CLKIN_DIV
(Host Mode)
1
1
shows how the user should pull down or pull up the reset configuration
Table 4-6. SYS_CLK_IN Division
(Agent Mode)
Frequency
PCI_CLK
33 MHz
66 MHz
Description
0000
(RCW loaded from NOR
Flash)
1000–1100
(use hard coded RCW)
CFG_RESET_
SOURCE[0:3]
Table
4-7. As a PCI host, the
Reset, Clocking, and Initialization
Reset Sequence
SYS_CLK_IN/
Duration in
PCI_CLK
Cycles
15210
15380
Duration
456
231
μ
μ
4-11
s
s