MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1016

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
host controller automatically moving to the next page pointer (that is, C_Page) when necessary. There are
three conditions for how the host controller handles C_Page.
Note that the only valid adjustment the host controller may make to C_Page is to increment by one.
16.6.10.2 Adding Interrupt Queue Heads to the Periodic Schedule
The link path(s) from the periodic frame list to a queue head establishes in which frames a transaction can
be executed for the queue head. Queue heads are linked into the periodic schedule so they are polled at the
appropriate rate. System software sets a bit in a queue head's S-Mask to indicate which micro-frame within
a 1 millisecond period a transaction should be executed for the queue head. Software must ensure that all
queue heads in the periodic schedule have S-Mask set to a non-zero value. An S-mask with a zero value
in the context of the periodic schedule yields undefined results.
If the desired poll rate is greater than one frame, system software can use a combination of queue head
linking and S-Mask values to spread interrupts of equal poll rates through the schedule so that the periodic
bandwidth is allocated and managed in the most efficient manner possible. Some examples are illustrated
in
16.6.10.3 Managing Transfer Complete Interrupts from Queue Heads
The host controller sets an interrupt to be signaled at the next interrupt threshold when the completed
transfer (qTD) has an Interrupt on Complete (IOC) bit set, or whenever a transfer (qTD) completes with a
short packet. If system software needs multiple qTDs to complete a client request (that is, like a control
transfer) the intermediate qTDs do not require interrupts. System software may only need a single interrupt
to notify it that the complete buffer has been transferred. System software may set IOC's to occur more
frequently. A motivation for this may be that it wants early notification so that interface data structures can
be re-used in a timely manner.
16-88
0, 2, 4, 6, 8, ....
S-Mask = 0x01
0, 2, 4, 6, 8, ...
S-Mask = 0x02
Table
•
•
•
Reference
Sequence
Frame #
The current transaction does not span a page boundary. The value of C_Page is not adjusted by the
host controller.
The current transaction does span a page boundary. The host controller must detect the page cross
condition and advance to the next buffer while streaming data to/from the USB.
The current transaction completes on a page boundary (that is, the last byte moved for the current
transaction is the last byte in the page for the current page pointer). The host controller must
increment C_Page before writing back status for the transaction.
16-66.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 16-66. Example Periodic Reference Patterns for Interrupt Transfers
A queue head for the bInterval of 2 milliseconds (16 micro-frames) is linked into the periodic schedule so
that it is reachable from the periodic frame list locations indicated in the previous column. In addition, the
S-Mask field in the queue head is set to 0x01, indicating that the transaction for the endpoint should be
executed on the bus during micro-frame 0 of the frame.
Another example of a queue head with a bInterval of 2 milliseconds is linked into the periodic frame list at
exactly the same interval as the previous example. However, the S-Mask is set to 0x02 indicating that the
transaction for the endpoint should be executed on the bus during micro-frame 1 of the frame.
Description
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