MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 324

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

e300 Processor Core Overview
Figure 7-1
LSU, and SRU—operate independently and in parallel. It should be noted that this is a conceptual diagram
and does not attempt to show how these features are physically implemented on the device.
The e300 core provides address translation and protection facilities, including an ITLB, DTLB, and
instruction and data BAT arrays. Instruction fetching and issuing are handled in the instruction unit.
Translation of addresses for cache or external memory accesses are handled by the MMUs. Both units are
discussed in more detail in
Units (MMUs).”
7.1.2
As shown in
unit, and BPU, provides centralized control of instruction flow to the execution units. The instruction unit
determines the address of the next instruction to be fetched based on information from the sequential
fetcher and from the BPU.
The instruction unit fetches the instructions from the instruction cache into the instruction queue. The BPU
receives branch instructions from the fetcher and uses static branch prediction to allow fetching from a
predicted instruction stream while a conditional branch is evaluated. The BPU folds out for unconditional
branch instructions and conditional branch instructions unaffected by instructions in the execution
pipeline.
Instructions issued beyond a predicted branch cannot complete execution until the branch is resolved,
preserving the programming model of sequential execution. If any of these are branch instructions, they
are decoded but not issued. Instructions to be executed by the FPU, IU, LSU, and SRU are issued and
allowed to progress up to the register write-back stage. Write-back is allowed when a correctly predicted
branch is resolved, and execution continues along the predicted path.
If branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and instructions
are issued from the correct path.
7.1.2.1
The instruction queue (IQ), shown in
instructions from the instruction unit during a single cycle. The instruction fetch unit continuously loads
as many instructions as space in the IQ allows. Instructions are dispatched to their respective execution
units from the dispatch unit at a maximum rate of two instructions per cycle. Dispatching is facilitated to
the IUs, FPU, LSU, and SRU by the provision of a reservation station at each unit. The dispatch unit
performs source and destination register dependency checking, determines dispatch serializations, and
inhibits subsequent instruction dispatching as required.
For a more detailed overview of instruction dispatch, see
7-6
•
Debug features
— Breakpoint status recorded in DBCR and IBCR control registers
— Two signals for the debug interface: stopped and ext_halt
— Performance monitor registers for system analysis in the e300c3
provides a block diagram of the e300 core that shows how the execution units—IU, FPU, BPU,
Instruction Unit
Figure
Instruction Queue and Dispatch Unit
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
7-1, the e300 core instruction unit, containing a fetch unit, instruction queue, dispatch
Section 7.1.2, “Instruction Unit,”
Figure
7-1, holds as many as six instructions and loads up to two
Section 7.3.6, “Instruction Timing.”
and
Section 7.1.5.1, “Memory Management
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