MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 829

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 15-109
reserved.
Freescale Semiconductor
Offset eTSEC1:0x2_4E00
Reset
Reset
6–15
Bits
16
17
0
1
3
4
5
W
W
R
R
ALM1P ALM2P
RTPE
16
0
0
0
PERIOD
ALM1P
ALM2P
TCLK_
Name
RTPE
PP1L
PP2L
FRD
FS
describes the fields of the TMR_CTRL register. Register fields not described below are
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
FRD
17
1
0
0
Alarm1 output polarity
0 active high output
1 active low output
Alarm2 output polarity
0 active high output
1 active low output
FIPER start indication
0 Fiper is enabled through timer enable
1 Fiper is enabled through timer enable and alarm indication.
Fiper1 pulse loopback mode enabled.
0 Trigger1 input is based upon normal external trigger input.
1 Fiper1 pulse is looped back into Trigger1 input.
Fiper2 pulse loopback mode enabled.
0 Trigger2 input is based upon normal external trigger input.
1 Fiper2 pulse is looped back into Trigger2 input.
1588 timer reference clock period. The timer clock counter will increment by TCLK_PERIOD every time
the accumulator register overflows. This clock period must be larger than the clock period of the timer
reference clock. For applications where user does not want the clock period to be added, they can
program this field to 1 to count the clock ticks. This field defaulted to 1 to count overflow ticks.
For nanosecond granularity on 1588 timer counter rate, the TCLK_PERIOD should be calculated using
the following equation:
Record Tx Timestamp to PAL Enable.
When set, and FCB[PTP] is set, the 8-byte timestamp for the packet is written to the PAL located in
external memory location at an offset of 16 bytes from the start of the Data Buffer Pointer of the first
TxBD. For guidelines on using the RTPE bit, refer to
Transmit
FIPER Realignment Disable
0 Fiper Realignment is enabled.
1 Fiper Realignment is disabled.
—
18
0
0
2
TCLK_PERIOD = 10
Table 15-109. TMR_CTRL Register Field Descriptions
FS
19
0
0
3
Packets.”
Figure 15-105. TMR_CTRL Register Definition
ESFDP ESFDE ETEP2 ETEP1 COPH CIPH TMSR
PP1L
20
0
0
4
9
PP2L
/Nominal_Frequency
21
5
0
0
22
0
0
6
23
Description
0
0
Section 15.6.6.5, “Timestamp Insertion on
24
0
0
TCLK_PERIOD
Enhanced Three-Speed Ethernet Controllers
25
0
0
26
0
0
27
0
0
BYP
28
0
0
Access: Mixed
TE
29
0
0
CKSEL
30
0
0
15-111
15
31
1
1