MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1090

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

I
17.3.1.2
Figure 17-3
Table 17-5
Although it describes the ratio between the I
controller clock and CSB is 1:1 (I
frequency). This ratio is set in SCCR[ENCCM]. Clock ratios of I
I
17-6
2
2
C Interfaces
C2 is not and it is always 1:1 with CSB. Consider this factor when selecting an FDR value.
Bits
0–1
2–7
Name
FDR
—
describes the bit settings of I2CnFDR. It also maps I2CnFDR[FDR] to the clock divider values.
shows the bits of the I
Offset 0x0_3004
Reset
I
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
C n Frequency Divider Register (I2C n FDR)
Reserved, should be cleared
Frequency divider ratio. Used to prescale the clock for bit-rate selection. The serial bit clock frequency of
SCL n is equal to the I
selections are described as follows:
FDR Divider (Decimal)
0x00 384
0x01 416
0x02 480
0x03 576
0x04 640
0x05 704
0x06 832
0x07 1024
0x08 1152
0x09 1280
0x0A 1536
0x0B 1920
0x0C 2304
0x0D 2560
0x0E 3072
0x0F 3840
0x10 4608
0x11 5120
0x12 6144
0x13 7680
0x14 9216
0x15 10240
Note: The value’s shown in the table are applicable only for the default value of DFSRR. Refer to AN2919.
W
R
0
Figure 17-3. I
—
1
Table 17-5. I2C n FDR Field Descriptions
2
2
2
C n controller clock divided by the divider. The serial bit clock frequency divider
C controller clock frequency is three times slower than CSB clock
Cn frequency divider register.
2
C n Frequency Divider Register (I2C n FDR)
2
2
C controller internal clock and SCL, the default ratio of I
FDR Divider (Decimal)
0x16 12288
0x17 15360
0x18 18432
0x19 20480
0x1A 24576
0x1B 30720
0x1C 36864
0x1D 40960
0x1E 49152
0x1F 61440
0x20 256
0x21 288
0x22 320
0x23 352
0x24 384
0x25 448
0x26 512
0x27 576
0x28 640
0x29 768
0x2A 896
All zeros
Description
FDR
2
C1 are controllable but clock ratio for
FDR Divider (Decimal)
0x2B 1024
0x2C 1280
0x2D 1536
0x2E 1792
0x2F 2048
0x30 2560
0x31 3072
0x32 3584
0x33 4096
0x34 5120
0x35 6144
0x36 7168
0x37 8192
0x38 10240
0x39 12288
0x3A 14336
0x3B 16384
0x3C 20480
0x3D 24576
0x3E 28672
0x3F 32768
Access: Read/write
Freescale Semiconductor
7
2
C