MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1034

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
When the endpoint is an isochronous OUT, there are only start-splits, and no complete-splits. When the
endpoint is an isochronous IN, there is at most one start-split and one to N complete-splits. The scheduling
boundary cases are:
A subset of the same mechanisms employed by full- and low-speed interrupt queue heads are employed
in siTDs to schedule and track the portions of isochronous split transactions. The following fields are
initialized by system software to instruct the host controller when to execute portions of the split
transaction protocol:
16-106
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Case 1: The entire split transaction is completely bounded by an H-Frame. For example, the
start-splits and complete-splits are all scheduled to occur in the same H-Frame.
Case 2a: This boundary case is where one or more (at most two) complete-splits of a split
transaction IN are scheduled across an H-Frame boundary. This can only occur when the split
transaction has the possibility of moving data in B-Frame, micro-frames 6 or 7 (H-Frame
micro-frame 7 or 0). When an H-Frame boundary wrap condition occurs, the scheduling of the split
transaction spans more than one location in the periodic list.(for example, it takes two siTDs in
adjacent periodic frame list locations to fully describe the scheduling for the split transaction).
Although the scheduling of the split transaction may take two data structures, all of the
complete-splits for each full-speed IN isochronous transaction must use only one data pointer. For
this reason, siTDs contain a back pointer.
Software must never schedule full-speed isochronous OUTs across an H-Frame boundary.
Case 2b: This case can only occur for a very large isochronous IN. It is the only allowed scenario
where a start-split and complete-split for the same endpoint can occur in the same micro-frame.
Software must enforce this rule by scheduling the large transaction first. Large is defined to be
anything larger than 579 byte maximum packet size.
SplitXState. This is a single bit residing in the Status field of an siTD (see
used to track the current state of the split transaction. The rules for managing this bit are described
in
Frame S-mask. This is a bit-field wherein system software sets a bit corresponding to the
micro-frame (within an H-Frame) that the host controller should execute a start-split transaction.
This is always qualified by the value of the SplitXState bit. For example, referring to the IN
example in
if the siTD is traversed by the host controller, and the SplitXState indicates Do Start Split, and the
current micro-frame as indicated by FRINDEX[2–0] is 0, then execute a start-split transaction.
Frame C-mask. This is a bit-field where system software sets one or more bits corresponding to the
micro-frames (within an H-Frame) that the host controller should execute complete-split
transactions. The interpretation of this field is always qualified by the value of the SplitXState bit.
For example, referring to the IN example in
of 0b 0011_1100 indicating that if the siTD is traversed by the host controller, and the SplitXState
indicates Do Complete Split, and the current micro-frame as indicated by FRINDEX[2–0] is 2, 3,
4, or 5, then execute a complete-split transaction.
Back Pointer. This field in a siTD is used to complete an IN split-transaction using the previous
H-Frame's siTD. This is only used when the scheduling of the complete-splits span an H-Frame
boundary.
Section 16.6.12.3.3, “Split Transaction Execution State Machine for Isochronous.”
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure
16-57, case 1, the S-mask would have a value of 0b0000_0001 indicating that
Figure
16-57, case 1, the C-mask would have a value
Table
Freescale Semiconductor
16-49). This bit is