MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 360

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Integrated Programmable Interrupt Controller (IPIC)
The interrupt sources controlled by the IPIC unit cause exceptions in the processor core. The internal
interrupt (int) signal is the main interrupt output from the IPIC to the core and it causes the regular interrupt
exception. The cint signal is the critical interrupt output from the IPIC to the processor core and causes the
critical interrupt exception. The smi signal is the system management interrupt output from the IPIC to the
processor core and causes the system management interrupt exception. The machine check exception is
caused by the internal mcp signal generated by the IPIC, informing the host processor of error conditions,
assertion of the external IRQ0 machine-check request (enabled when SEMSR[SIRQ0] = 1), and other
conditions.
Table 8-1
IPIC unit.
The IPIC receives interrupt request signals from the following two sources:
The unit selects the highest priority interrupt from all current interrupts and forwards it to the internal
processor core, or off-chip for external servicing.
The IPIC also manages an internal non-maskable machine-check processor (mcp) signal and the interrupt
generated by the off-chip interrupt sources (IRQ[0:4]).
The interrupt router of the IPIC monitors the outputs of the internal configuration registers. When the
priority is highest in one of the received interrupt signals, the IPIC sets the corresponding bit in one of the
interrupt pending registers—system internal interrupt pending register
pending register (SEPNR). If the interrupt is not masked, the IPIC asserts the int signal to indicate an
interrupt request to the processor. When the processor is running the specific int, cint, or smi interrupt
handler code, the processor must vectorize the external interrupt handler by explicitly (in software) reading
the corresponding interrupt vector register (SIVCR, SCVCR, or SMVCR). In response to this read, the
IPIC unit returns the vector (associated with the interrupt source) to the interrupt handler routine. In
addition, the handler can vectorize different branches of interrupt handling.
8-2
•
•
External to the integrated device
Internal to the integrated device
shows the relationship of the various functional blocks and external signals of the device to the
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
(
SIPNR)/system external interrupt
Freescale Semiconductor