MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 724

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.4
This section defines the eTSEC interface signals. The buses are described using the bus convention used
in IEEE 802.3 because the PHY follows this same convention. (That is, TxD[3:0] means 0 is the lsb.) Note
that except for external physical interfaces the buses and registers follow a big-endian format, where 0
denotes the msb.
Each eTSEC network interface supports multiple options:
Table 15-1
15-6
TSEC n _GTX_CLK
EC_GTX_CLK125
TSEC n _RXD[3:0]
TSEC n _RX_CLK
TSEC n _RX_DV
•
•
•
•
•
Signal Name
TSEC n _COL
TSEC n _CRS
EC_MDIO
EC_MDC
Internal loop back supported for all interfaces except when configured for half-duplex operation
Internal loop back mode is selected through the loop back bit in the MACCFG1 register. See
Section 15.7.1, “Interface Mode Configuration,”
The MII option requires 18 I/O signals (including the MDIO and MDC MII management interface)
and supports both a data and a management interface to the PHY (transceiver) device. The MII
option supports both 10- and 100-Mbps Ethernet rates.
The RGMII, RTBI, and RMII options are reduced-pin implementations of the GMII, TBI, and MII
interfaces, respectively.
SGMII interfaces are offered via the SerDes interface signals.
1588 timer signals
External Signals Description
lists the network interface signals.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
MII—collision, input
MII—carrier sense, input
RTBI, RGMII—inverted transmit clock feedback, output
MII, RMII—transmit clock feedback when transmission is enabled, zero otherwise, output
Oscillator source for RGMII, RTBI transmit clock, input, shared by all eTSECs
Management clock, output.
Management data, bidirectional.
MII, RGMII—receive clock, input
MII—receive data valid, input
RGMII (RX_CLK rising)—receive data valid, input
RGMII (RX_CLK falling)—receive error, input
RTBI (RX_CLK rising)—receive code group (RCG) bit 4, input
RTBI (RX_CLK falling)—receive code group (RCG) bit 9, input
RMII—CRS_DV carrier sense/data valid, input
MII—Receive data bits 3:0, input
RGMII (RX_CLK rising) —Receive data bits 3:0, input
RGMII (RX_CLK falling)—Receive data bits 7:4, input
RTBI (RX_CLK rising)—RCG bits 3:0, input
RTBI (RX_CLK falling)—RCG bits 8:5, input
RMII—RXD[1:0] receive data bits, input
RMII—RXD[3:2] are unused
Table 15-1. eTSEC n Network Interface Signal Properties
Function
for details.
Freescale Semiconductor
Hi-Z (input)
Reset
State
—
—
—
—
—
—
0
0